Semiconductor device having a glass substrate core layer
Disclosed are a packaging substrate and a semiconductor device. The semiconductor device includes an element unit including a semiconductor element and a packaging substrate electrically connected to the element unit. By applying a glass substrate to the packaging substrate as a core substrate, connecting the semiconductor element and a motherboard can be closer to each other, so that electrical signals are transferred through as short a path, and significantly improved electrical properties such as a signal transfer rate could be achieved. Also, it is possible to prevent an occurrence of a parasitic element effect and to apply to a high-speed circuit device without additional insulating process.
1. A semiconductor device comprising:
an element unit comprising a semiconductor element; and
a packaging substrate, electrically connected to the element unit,
wherein the packaging substrate comprises:
a core layer comprising a glass substrate having a first surface opposing a second surface, a plurality of core vias, each having a varying diameter, passing through the glass substrate in a thickness direction thereof, and a core distribution layer comprising a core conductive layer disposed on a surface of core vias electrically connecting through the core vias between a conductive layer of the first surface and a conductive layer of the second surface; and
an upper layer, disposed on the first surface, and comprising an upper conductive layer configured to externally connect the core distribution layer.
2. The semiconductor device of claim 1 , wherein an organic substrate is substantially excluded from the packaging substrate.
3. The semiconductor device of claim 1 , further comprising a board unit placed under the packaging substrate,
wherein any substrate other than the glass substrate is not applied between the element unit and the board unit.
4. The semiconductor device of claim 1 , wherein a surface conductive layer is disposed on a surface of the glass substrate and has an adhesive strength of 3N/cm or more with respect to the glass substrate.
5. The semiconductor device of claim 1 , wherein a diameter of an upper end and a diameter of a lower end of each of the plurality of vias are substantially equal.
6. The semiconductor device of claim 1 , wherein a diameter of an upper end and a diameter of a lower end of each of the plurality of vias are different.
7. The semiconductor device of claim 1 , wherein a diameter of an intermediate portion and a diameter of a lower end of each of the plurality of vias are different.
8. The semiconductor device of claim 7 , wherein the diameter of the intermediate portion and a diameter of an upper end of each of the plurality of vias are different.
9. The semiconductor device of claim 1 , wherein the core conductive layer disposed on the surface of core vias has a through hole formed therethrough.
10. A packaging substrate comprising:
a core layer comprising a glass substrate having a first surface opposing a second surface, a plurality of core vias, each having a varying diameter, passing through the glass substrate in a thickness direction thereof, and a core distribution layer comprising a core conductive layer disposed on a surface of surface of the core via electrically connecting through the core vias between a conductive layer of the first surface and a conductive layer of the second surface; and
an upper layer disposed on the first surface, and comprising an upper conductive layer configured to externally connect the core distribution layer,
wherein an organic substrate is substantially excluded from the packaging substrate.
11. The packaging substrate of claim 10 , wherein a surface conductive layer is disposed on a surface of the glass substrate and has an adhesive strength of 3N/cm or more with respect to the glass substrate.
12. The packaging substrate of claim 10 , wherein a diameter of an upper end and a diameter of a lower end of each of the plurality of vias are substantially equal.
13. The packaging substrate of claim 10 , wherein a diameter of an upper end and a diameter of a lower end of each of the plurality of vias are different.
14. The packaging substrate of claim 10 , wherein a diameter of an intermediate portion and a diameter of a lower end of each of the plurality of vias are different.
15. The packaging substrate of claim 14 , wherein the diameter of the intermediate portion and a diameter of an upper end of each of the plurality of vias are different.
16. The packaging substrate of claim 10 , wherein the core conductive layer disposed on the surface of core vias has a through hole formed therethrough.