METHODS AND APPARATUS FOR EMBEDDED ANTIFUSES
Methods and apparatus for forming an embedded antifuse in a wafer-level packaging compatible process. In some embodiments, a method for forming an embedded antifuse includes forming a first redistribution layer on a first polymer layer, depositing an antifuse dielectric layer on the first redistribution layer, forming a second polymer layer on the antifuse dielectric layer, creating at least one first via through the second polymer layer to the antifuse dielectric layer using a lithography process with, for example, a dielectric etch, and forming a second redistribution layer on the second polymer layer and contacting the antifuse dielectric layer at a bottom of the at least one first via.
1 . A method of constructing an embedded antifuse in a wafer-level packaging compatible process, comprising:
forming a first redistribution layer on a first polymer layer;
depositing an antifuse dielectric layer on the first redistribution layer;
forming a second polymer layer on the antifuse dielectric layer;
creating at least one via through the second polymer layer to the antifuse dielectric layer using a lithography process; and
forming a second redistribution layer on the second polymer layer and contacting the antifuse dielectric layer at a bottom of the at least one via.
2 . The method of claim 1 , further comprising:
removing a portion of the antifuse dielectric layer after deposition from a surface of the first polymer layer and the first redistribution layer.
3 . The method of claim 1 , further comprising:
forming at least one of the first redistribution layer or the second redistribution layer using a semi-additive process (SAP).
4 . The method of claim 1 comprising a fan-in or fan-out wafer-level packaging compatible process.
5 . The method of claim 1 , further comprising:
depositing an antifuse dielectric layer comprising a material based on at least one of amorphous silicon, silicon nitride, silicon oxide, silicon carbide, or metal oxide.
6 . The method of claim 1 , further comprising:
forming at least one of the first polymer layer or the second polymer layer from a material based on at least one of polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), epoxy, or photo-sensitive material.
7 . A method of constructing an embedded antifuse in a wafer-level packaging compatible process, comprising:
forming a first redistribution layer on a first polymer layer;
forming a second polymer layer on the first redistribution layer;
creating at least one via through the second polymer layer to the first redistribution layer using a lithography process;
depositing an antifuse dielectric layer on the second polymer layer and in the at least one via, contacting the first redistribution layer at a bottom of the at least one via; and
forming a second redistribution layer on the second polymer layer and the antifuse dielectric layer.
8 . The method of claim 7 , further comprising:
removing a portion of the antifuse dielectric layer after deposition from a surface of the second polymer layer.
9 . The method of claim 7 , further comprising:
forming at least one of the first redistribution layer or the second redistribution layer using a semi-additive process (SAP).
10 . The method of claim 7 comprising a fan-in or fan-out wafer-level packaging compatible process.
11 . The method of claim 7 , further comprising:
depositing an antifuse dielectric layer comprising a material based on at least one of amorphous silicon, silicon nitride, silicon oxide, silicon carbide, or metal oxide.
12 . The method of claim 7 , further comprising:
forming at least one of the first polymer layer or the second polymer layer from a material based on at least one of polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), epoxy, or photo-sensitive material.
13 . The method of claim 7 , further comprising:
forming a plurality of second polymer layers on the first redistribution layer;
creating the at least one via through the plurality of second polymer layers to the first redistribution layer using a lithography and dry etch process;
depositing the antifuse dielectric layer on an uppermost surface of the plurality of second polymer layers and in the at least one via, the antifuse dielectric layer contacting the first redistribution layer at a bottom of the at least one via; and
forming the second redistribution layer on the plurality of second polymer layers, the second redistribution layer contacting the antifuse dielectric layer at least on a side of the at least one via and at the bottom of the at least one via.
14 . The method of claim 13 , further comprising:
removing a portion of the antifuse dielectric layer after deposition from the uppermost surface of the plurality of second polymer layers.
15 . The method of claim 13 , further comprising:
forming at least one of the first redistribution layer or the second redistribution layer using a semi-additive process (SAP).
16 . The method of claim 13 comprising a fan-in or fan-out wafer-level packaging compatible process.
17 . The method of claim 13 , further comprising:
depositing an antifuse dielectric layer comprising a material based on at least one of amorphous silicon, silicon nitride, silicon oxide, silicon carbide, or metal oxide.
18 . The method of claim 13 , further comprising:
forming at least one of the first polymer layer or at least one of the plurality of second polymer layers from a material based on at least one of polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), epoxy, or photo-sensitive material.
19 . The method of claim 13 , further comprising:
etching a portion of the antifuse dielectric layer after deposition from the uppermost surface of the plurality of second polymer layers.
20 . An apparatus for an embedded antifuse, comprising:
a first redistribution layer formed on a first polymer layer;
a plurality of second polymer layers formed on the first redistribution layer and the first polymer layer;
at least one via extending from a top surface of one of the plurality of second polymer layers to the first redistribution layer;
an antifuse dielectric layer formed in the at least one via and on the first redistribution layer at a bottom of the at least one via; and
a second redistribution layer formed at least on the antifuse dielectric layer in at least the at least one via.