Magnetoresistive random access memory
A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
1. A semiconductor device, comprising:
a metal-oxide semiconductor (MOS) transistor on a substrate;
an interlayer dielectric (ILD) layer on the MOS transistor; and
a magnetic tunneling junction (MTJ) on the ILD layer, wherein a top surface of the MTJ is electrically connected to a source/drain region of the MOS transistor and a top surface of a top electrode of the MTJ comprises a reverse V-shape.
2. The semiconductor device of claim 1 , further comprising:
a first metal interconnection connected to a bottom surface of the MTJ;
a first inter-metal dielectric (IMD) layer on the ILD layer and around the first metal interconnection;
a second metal interconnection adjacent to the MTJ;
a second IMD layer on the first IMD layer and around the MTJ and the second metal interconnection;
a third metal interconnection connected to a bottom surface of the first metal interconnection;
a fourth metal interconnection connected to a bottom surface of the second metal interconnection and the source/drain region of the MOS transistor;
a fifth metal interconnection connected to the top surface of the MTJ and the second metal interconnection; and
a third IMD layer on the second IMD layer and around the fifth metal interconnection.
3. The semiconductor device of claim 2 , wherein the second metal interconnection comprises:
a first trench conductor; and
a first via conductor connected to a bottom surface of the first trench conductor.
4. The semiconductor device of claim 3 , wherein top surfaces of the first trench conductor and the second IMD layer are coplanar.
5. The semiconductor device of claim 3 , wherein the fifth metal interconnection comprises:
a second trench conductor; and
a second via conductor and a third via conductor under the second trench conductor, wherein the second via conductor is connected to the first trench conductor and the third via conductor is connected to the MTJ.
6. The semiconductor device of claim 5 , wherein top surfaces of the second trench conductor and the third IMD layer are coplanar.
7. The semiconductor device of claim 5 , wherein a bottom surface of the second via conductor comprises a planar surface.
8. The semiconductor device of claim 5 , wherein a bottom surface of the third via comprises a reverse V-shape.
9. The semiconductor device of claim 1 , wherein a top surface of the MTJ comprises a reverse V-shape.