IP Library Granted Patent US 10,923,497
Granted Patent B2
US 10,923,497 · App. 16/298,923 · Granted Feb 16, 2021

Electronic device having stacked structures and method for manufacturing the same

Inventors: Ki Hong Lee (Gyeonggi-do, KR); Ji Yeon Baek (Gyeonggi-do, KR); Seung Ho Pyi (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L27/11582H01L21/76898H01L27/1157H01L27/11565
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Quick Facts
Patent No.
US 10,923,497
App. No.
16/298,923
Granted
Feb 16, 2021
Kind
B2
Abstract

A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

Claims (46)

1. A method of manufacturing an electronic device, the method comprising:

forming a first stacked structure;

forming a first pillar passing through the first stacked structure;

forming a first sacrificial layer on the first stacked structure;

forming an insulating layer on the first sacrificial layer;

forming a trench in the insulating layer;

forming a second sacrificial layer in the trench;

forming a second stacked structure on the second sacrificial layer and the insulating layer; and

forming a second pillar passing through the second stacked structure and contacting the second sacrificial layer.

2. The method of claim 1 , wherein the first sacrificial layer includes an oxide material.

3. The method of claim 1 , wherein the second sacrificial layer includes polysilicon.

4. The method of claim 1 , wherein the first stacked structure includes first polysilicon layers and first oxide layers alternately stacked.

5. The method of claim 4 , further comprising:

forming first data storage layers interposed between the first pillar and the first polysilicon layers, wherein the first data storage layers include silicon.

6. The method of claim 1 , wherein the second stacked structure includes second polysilicon layers and second oxide layers alternately stacked.

7. The method of claim 6 , further comprising:

forming second data storage layers interposed between the second pillar and the second polysilicon layers, wherein the second data storage layers include silicon.

8. The method of claim 1 , wherein the insulating layer is located at substantially the same level as the second sacrificial layer.

9. The method of claim 1 , wherein the insulating layer has substantially the same thickness as the second sacrificial layer.

10. The method of claim 1 , wherein the insulating layer surrounds sidewalls of the second sacrificial layer.

11. The method of claim 1 , wherein the second sacrificial layer contacts the first sacrificial layer.

12. A method of manufacturing an electronic device, the method comprising:

forming a first stacked structure including first polysilicon layers and first oxide layers alternately stacked;

forming first data storage layers and a first pillar, wherein the first passes through the first stacked structure, and the first data storage layers are interposed between the first pillar and the first polysilicon layers;

forming a first sacrificial layer on the first stacked structure;

forming an insulating layer on the first sacrificial layer;

forming a trench in the insulating layer;

forming a second sacrificial layer in the trench;

forming a second stacked structure on the second sacrificial layer and the insulating layer; and

forming a second pillar passing through the second stacked structure and contacting the second sacrificial layer.

13. The method of claim 12 , wherein the first sacrificial layer includes an oxide material.

14. The method of claim 12 , wherein the second sacrificial layer includes polysilicon.

15. The method of claim 12 , wherein the first stacked structure includes first polysilicon layers and first oxide layers alternately stacked.

16. A method of manufacturing an electronic device, the method comprising:

forming a first stacked structure;

forming a first pillar passing through the first stacked structure;

forming a first sacrificial layer on the first stacked structure;

forming an insulating layer on the first sacrificial layer;

forming a trench in the insulating layer;

forming a second sacrificial layer in the trench to contact the first sacrificial layer;

forming a second stacked structure on the second sacrificial layer and the insulating layer; and

forming a second pillar passing through the second stacked structure and contacting the second sacrificial layer.

17. The method of claim 16 , wherein the first sacrificial layer includes an oxide material.

18. The method of claim 16 , wherein the second sacrificial layer includes polysilicon.

19. The method of claim 16 , wherein the first stacked structure includes first polysilicon layers and first oxide layers alternately stacked.

20. The method of claim 1 , wherein the insulating layer is located between the first sacrificial layer and the second stacked structure.

Priority Claims (1)
KR 10-2014-0192025 · Dec 29, 2014 · national
Continuity (4)
Continuation 15821388 · Nov 22, 2017
Continuation 15398467 · Jan 4, 2017
Division 14732390 · Jun 5, 2015
Related Publication 20190206892A1 · Jul 4, 2019