IP Library Granted Patent US 10,826,488
Granted Patent B2
US 10,826,488 · App. 16/299,843 · Granted Nov 3, 2020

Switch device with switch circuits that provide high voltage surge protection

Inventors: Lei Huang (Sunnyvale, CA); Na Meng (Beijing, CN); Kenneth P. Snowdon (Falmouth, ME)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H03K17/687H02H3/202
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Quick Facts
Patent No.
US 10,826,488
App. No.
16/299,843
Granted
Nov 3, 2020
Kind
B2
Abstract

A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its gate.

Claims (47)

1. A switch device comprising:

a switch path that connects a first node to a second node, the switch path comprising a switch circuit, the switch circuit comprising:

a first transistor disposed along the switch path,

a voltage divider circuit configured to provide a voltage corresponding to an average of a drain voltage of the first transistor and a source voltage of the first transistor to the bulk of the first transistor when the first transistor is turned on, and

a first Zener diode having a first end connected to a gate of the first transistor and a second end connected to the bulk of the first transistor,

wherein the switch circuit is configured to automatically connect the bulk of the first transistor to either a drain of the first transistor or a source of the first transistor to turn OFF the first transistor and open the switch path in response to a surge voltage on the switch path.

2. The switch device of claim 1 , wherein the switch circuit is configured to automatically connect the bulk of the first transistor to the drain of the first transistor to withstand a positive surge voltage on the switch path.

3. The switch device of claim 1 , wherein the switch circuit is configured to automatically connect the bulk of the first transistor to the source of the first transistor to withstand a negative surge voltage on the switch path.

4. The switch device of claim 1 , wherein the switch circuit further comprises:

a cross-coupling circuit that is configured to automatically connect the bulk of the first transistor to either the source of the first transistor or the drain of the first transistor based on a polarity of the surge voltage.

5. The switch device of claim 1 , wherein the switch circuit further comprises:

a gate control driver that is connected to the gate of the first transistor and is configured to turn the transistor ON or OFF in response to an enable signal.

6. The switch device of claim 1 , wherein the voltage divider circuit comprises:

a second transistor having a drain coupled to a source of the first transistor, a source coupled to a bulk of the first transistor, and a gate connected to a gate of the first transistor; and

a third transistor having a source coupled to a drain of the first transistor, a drain coupled to a bulk of the first transistor, and a gate connected to a gate of the first transistor.

7. The switch device of claim 1 , wherein the first end of the first Zener diode is a cathode of the first Zener diode, and the second end of the first Zener diode is an anode of the first Zener diode.

8. A method of connecting nodes of a switch device, the method comprising:

connecting a common node to a first end node through a switch path that comprises a first transistor;

automatically connecting a bulk of the first transistor to either a source of the first transistor or a drain of the first transistor depending on a potential on the source of the first transistor relative to a potential on the drain of the first transistor;

providing a voltage corresponding to an average of a drain voltage of the first transistor and a source voltage of the first transistor to the bulk of the first transistor when the first transistor is turned on; and

clamping a voltage at the gate of the first transistor at a clamping level in response to a surge voltage through the switch path.

9. The method of claim 8 , wherein the bulk of the first transistor is connected to the source of the first transistor to withstand a negative surge voltage on the switch path.

10. The method of claim 8 , wherein the bulk of the first transistor is connected to the drain of the first transistor to withstand a positive surge voltage on the switch path.

11. A switch device comprising:

a common node;

a switch path that connects the common node to a first end node, the switch path comprising a first transistor that is connected in series to a second transistor, a source of the first transistor is connected to a drain of the second transistor, and a bulk of the first transistor is connected to either the source of the first transistor or a drain of the first transistor depending on a potential on the source of the first transistor relative to a potential on the drain of the first transistor, the switch path comprising a switch circuit,

wherein the switch circuit comprises:

a first resistor;

a second resistor;

a first Zener diode having an anode connected to a bulk of the first transistor and a cathode connected to the drain of the first transistor through the first resistor;

a second Zener diode having an anode connected to the bulk of the first transistor and a cathode connected to the source of the first transistor through the second resistor;

a voltage divider comprising a first divider transistor coupled across the first Zener diode and a second divider transistor coupled across the second Zener diode,

wherein a drain of the first divider transistor is connected to a source of the first transistor, a source of the second divider transistor is connected to the drain of the first transistor, a source of the first divider transistor is connected to a drain of the second divider transistor, and a gate of the first divider transistor and a gate of the second divider transistor are both connected to the gate of the first transistor.

12. The switch device of claim 11 , wherein the drain of the first transistor is connected to the common node.

13. The switch device of claim 12 , wherein the drain of the third transistor is connected to the common node.

14. The switch device of claim 13 , wherein the drain of the third transistor is connected to the common node through the first transistor.

15. The switch device of claim 11 , wherein the source of the first transistor is connected to the bulk of the first transistor and the source of the second transistor is connected to the bulk of the second transistor to withstand a negative surge voltage on the switch path.

16. The switch device of claim 11 , wherein the drain of the first transistor is connected to the bulk of the first transistor and the drain of the second transistor is connected to the bulk of the second transistor to withstand a positive surge voltage on the switch path.

17. The switch device of claim 11 , wherein the first and second transistors comprise NMOS transistors.

18. The switch device of claim 11 , wherein the switch circuit further comprises:

a cross-coupling circuit that automatically connects the bulk of the first transistor to the source of the first transistor when the source of the first transistor has a lower potential compared to the drain of the first transistor and automatically connects the bulk of the first transistor to the drain of the first transistor when the drain of the first transistor has a lower potential compared to the source of the first transistor.

19. The switch device of claim 18 , wherein the cross-coupling circuit comprises:

a fifth transistor; and

a sixth transistor,

wherein a source of the fifth transistor is connected to a drain of the sixth transistor and to the bulk of the first transistor, a drain of the fifth transistor is connected to the source of the first transistor, a source of the sixth transistor is connected to the drain of the first transistor, a gate of the fifth transistor is connected to the drain of the first transistor, and a gate of the sixth transistor is connected to the source of the first transistor.

20. The switch device of claim 19 , wherein the switch circuit further comprises:

a gate control driver circuit that is connected to the gate of the first transistor and turns the first transistor ON or OFF in response to an enable signal.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2019
From: HUANG, LEI; MENG, NA; SNOWDON, KENNETH P.
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 048575/0306 →