IP Library Granted Patent US 10,982,324
Granted Patent B2
US 10,982,324 · App. 16/304,222 · Granted Apr 20, 2021

Method and device for producing coated semiconductor wafers

Inventor: Joerg Haberecht (Freiberg, DE)
Assignee: Siltronic AG
C23C16/4405C23C16/4558C23C16/45574H01L21/0262
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Quick Facts
Patent No.
US 10,982,324
App. No.
16/304,222
Granted
Apr 20, 2021
Kind
B2
Abstract

Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.

Claims (8)

1. A method for producing coated semiconductor wafers, comprising:

introducing a process gas through first gas inlet openings into a reactor chamber along a first flow direction and over a substrate wafer of semiconductor material lying on a susceptor, and

depositing a layer on the substrate wafer to produce a coated substrate wafer, wherein material precipitate derived from the process gas precipitates on a preheat ring arranged around the susceptor;

extracting the coated substrate wafer from the reactor chamber; and

following extracting the coated substrate wafer from the reactor chamber, removing material precipitate from the preheat ring by introducing an etching gas over the preheat ring through the first gas inlet openings into the reactor chamber along the first flow direction and also through second gas inlet openings, between which the first gas inlet openings are arranged, and which provides further flow directions for etching gas which intersect with the first flow direction.

2. The method of claim 1 , further comprising, before introducing the etching gas into the reactor chamber, repeating the deposition of a layer on a further substrate wafer of semiconductor material and extracting a further coated substrate wafer from the reactor chamber, and optionally repeating the steps with yet further substrate wafers until the material precipitate on the preheat ring has reached a minimum set thickness.

3. The method of claim 2 , wherein the etching gas contains hydrogen chloride, and the material precipitate on the preheat ring contains silicon, and has a minimum thickness of 50 μm prior to its removal from the preheat ring.

4. The method of claim 1 , wherein the step of depositing a layer on a substrate wafer comprises depositing an epitaxial layer of silicon on the substrate wafer.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2018
From: HABERECHT, JOERG
To: SILTRONIC AG
Reel/Frame 047693/0243 →