IP Library Granted Patent US 10,971,415
Granted Patent B2
US 10,971,415 · App. 16/305,146 · Granted Apr 6, 2021

Semiconductor device, manufacturing method for semiconductor device, semiconductor module, and power conversion device

Inventors: Kyoko Kojima (Tokyo, JP); Hiroyuki Matsushima (Tokyo, JP); Kazuhiro Suzuki (Tokyo, JP)
Assignee: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
H01L23/08H01L21/56H01L23/29H01L25/0655H01L29/1602H01L29/1608H01L29/2003H01L2224/48227
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Quick Facts
Patent No.
US 10,971,415
App. No.
16/305,146
Granted
Apr 6, 2021
Kind
B2
Abstract

In a semiconductor device using a wide bandgap semiconductor material having a bandgap larger than that of silicon, reliability of the semiconductor device is improved by achieving a structure in which electric field strength in the vicinity of an outer end portion of a semiconductor chip is relaxed. A side surface of the semiconductor chip CHP 1 a is formed of a region R 1 including a first corner, a region R 2 including a second corner, and a region R 3 interposed between the region R 1 and the region R 2 . At this point, in a case of defining a minimum film thickness of a high electric field-resistant sealing member MR in the region R 3 as t 1 and defining a maximum film thickness of the high electric field-resistant sealing member MR in the region R 1 as t 2 , a relation of t 2 ≤1.5×t 1 is satisfied.

Claims (37)

1. A semiconductor device comprising:

a semiconductor chip including a semiconductor material having a bandgap larger than a bandgap of silicon; and

a sealing member to seal the semiconductor chip;

wherein

the semiconductor chip includes an insulation member formed on a surface of the semiconductor substrate in side view and having a dielectric breakdown field strength higher than the sealing member,

a side surface of the semiconductor chip includes

a first region including a first corner;

a second region including a second corner; and

a third region interposed between the first region and the second region, and

a minimum film thickness of the insulation member in the third region t 1 is greater than a maximum film thickness of the insulation member in the first region t 2 such that t 2 <t 1 .

2. The semiconductor device according to claim 1 , wherein a relation of 0.5×t 1 ≤t 2 ≤1.2×t 1 is satisfied.

3. The semiconductor device according to claim 1 , wherein a relation of t 2 ≤120 μm is satisfied.

4. The semiconductor device according to claim 1 , wherein

the insulation member contains any one of a polyimide resin, a polyamideimide resin, a polyetheramideimide resin, and a polyetheramide resin, and

the sealing member consists of a silicone gel.

5. The semiconductor device according to claim 1 , wherein the semiconductor material is any one of silicon carbide, gallium nitride, and diamond.

6. A semiconductor module comprising a plurality of semiconductor chips according to claim 1 .

7. A power conversion device comprising a plurality of semiconductor modules according to claim 6 .

8. A manufacturing method for a semiconductor device, comprising steps of:

(a) preparing a semiconductor wafer that includes a semiconductor material having a bandgap larger than a bandgap of silicon and has a surface;

(b) applying a paste-state insulation material to a first application region and a second application region along a first direction of the surface; and

(c) applying a paste-state insulation material to the first application region and a third application region along a second direction crossing with the first direction on the surface,

wherein an application amount of the insulation material in the first application region is set smaller than an application amount of the insulation material in the second application region in the step (b).

9. The manufacturing method for a semiconductor device according to claim 8 , wherein the application amount of the insulation material in the first application region is set smaller than the application amount of the insulation material in the third application region in the step (c).

10. The manufacturing method for a semiconductor device according to claim 8 , wherein

the insulation material is applied by using a dispenser in the step (b), and

a movement speed of the dispenser in the first application region is set faster than a movement speed of the dispenser in the second application region in the step (b).

11. The manufacturing method for a semiconductor device according to claim 8 , wherein

the insulation material is applied by using a dispenser in the step (b), and

in the step (b), a pressure to discharge the insulation material from the dispenser is set to a first pressure in the second application region while a pressure to discharge the insulation material from the dispenser is set to a second pressure that is lower than the first pressure in the first application region.

12. The manufacturing method for a semiconductor device according to claim 8 , further comprising a step (d) of obtaining a semiconductor chip by dicing the semiconductor wafer after the step (c).

13. The manufacturing method for a semiconductor device according to claim 12 , further comprising a step (e) of sealing the semiconductor chip with a sealing member after the step (d).

14. A manufacturing method for a semiconductor device, comprising steps of:

(a) preparing a semiconductor wafer that includes a semiconductor material having a bandgap larger than a bandgap of silicon and has a surface;

(b) applying a paste-state insulation material to a second application region along a first direction of the surface while stepping over a first application region; and

(c) applying a paste-state insulation material to the first application region and a third application region along a second direction that crosses with the first direction on the surface,

wherein the paste-state insulation material is not applied to the first application region in the step (b).

Assignments (2)
CHANGE OF NAME Recorded Apr 30, 2025
From: HITACHI POWER SEMICONDUCTOR DEVICE LTD.
To: MINEBEA POWER SEMICONDUCTOR DEVICE INC.
Reel/Frame 071142/0232 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2018
From: KOJIMA, KYOKO; MATSUSHIMA, HIROYUKI; SUZUKI, KAZUHIRO
To: HITACHI POWER SEMICONDUCTOR DEVICE, LTD.
Reel/Frame 047640/0407 →
Priority Claims (1)
JP JP2016-118868 · Jun 15, 2016 · national
Continuity (1)
Related Publication 20200321258A1 · Oct 8, 2020