Shift register, gate driving circuit and driving method for the same, and liquid crystal display
A shift register, a gate driving circuit and a driving method for the same, and a liquid crystal display. The shift register includes: a pull-up sub-circuit configured to set a potential at a pull-up node to an operating potential when a first input signal is received via a first input terminal; a first output sub-circuit configured to output a gate driving signal at an output terminal according to a first clock signal received via a first clock signal terminal when the potential at the pull-up node is the operating potential; and a second output sub-circuit configured to output a gate driving signal at the output terminal when a second input signal is received via a second input terminal during a period other than a duration in which one frame of picture is displayed.
1. A shift register, comprising:
a pull-up sub-circuit coupled to a first input terminal and a pull-up node of the shift register, and configured to set a potential at the pull-up node to an operating potential when a first input signal is received via the first input terminal;
a first output sub-circuit coupled to the pull-up node, a first clock signal terminal, and an output terminal of the shift register, and configured to output a first gate driving signal at the output terminal according to a first clock signal received via the first clock signal terminal when the potential at the pull-up node is the operating potential;
a reset sub-circuit coupled to a reset terminal, the pull-up node, and the output terminal of the shift register, and configured to set potentials at the pull-up node and the output terminal to a reset potential when a reset signal is received via the reset terminal; and
a second output sub-circuit coupled to a second input terminal and the output terminal of the shift register, and configured to output a second gate driving signal at the output terminal when a second input signal is received via the second input terminal during a period other than a duration in which one frame of picture is displayed to set potentials at the pull-up node and a pull-down node of the shift register to the reset potential,
wherein the second output sub-circuit comprises:
a first output switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the second input terminal, the output terminal, and an operating potential terminal of the shift register, respectively;
a first pull-down switching element, a control terminal, a first terminal, and a second terminal of which are to coupled the second input terminal, a reset potential terminal, and the pull-up node of the shift register, respectively; and
a second pull-down switching component, a control terminal, a first terminal, and a second terminal of which are coupled to the second input terminal, the reset potential terminal, and the pull-down node of the shift register, respectively.
2. The shift register according to claim 1 , wherein the pull-up sub-circuit comprises:
a first pull-up switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the first input terminal, a second clock signal terminal, and the pull-up node of the shift register, respectively.
3. The shift register according to claim 2 , wherein the pull-up sub-circuit further comprises:
a second pull-up switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the first input terminal, the reset potential terminal, and the pull-down node of the shift register, respectively.
4. The shift register according to claim 1 , wherein the first output sub-circuit comprises:
a second output switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the pull-up node, the first clock signal terminal, and the output terminal of the shift register, respectively; and
a capacitor connected between the pull-up node and the output terminal.
5. The shift register according to claim 1 , wherein the reset sub-circuit comprises:
a first reset switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the reset terminal, the reset potential terminal, and the pull-up node of the shift register, respectively; and
a second reset switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the pull-down node, the reset potential terminal, and the output terminal of the shift register, respectively.
6. The shift register according to claim 5 , wherein the reset sub-circuit further comprises:
a third reset switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the reset terminal, the operating potential terminal, and the pull-down node of the shift register, respectively.
7. A gate driving circuit, comprising a plurality of cascaded shift registers, each of the shift registers comprising:
a pull-up sub-circuit coupled to a first input terminal and a pull-up node of the shift register, and configured to set a potential at the pull-up node to an operating potential when a first input signal is received via the first input terminal;
a first output sub-circuit coupled to the pull-up node, a first clock signal terminal, and an output terminal of the shift register, and configured to output a first gate driving signal at the output terminal according to a first clock signal received via the first clock signal terminal when the potential at the pull-up node is the operating potential;
a reset sub-circuit coupled to a reset terminal, the pull-up node, and the output terminal of the shift register, and configured to set potentials at the pull-up node and the output terminal to a reset potential when a reset signal is received via the reset terminal, and
a second output sub-circuit coupled to a second input terminal and the output terminal of the shift register, and configured to output a second gate driving signal at the output terminal when a second input signal is received via the second input terminal during a period other than a duration in which one frame of picture is displayed to set potentials at the pull-up node and a pull-down node of the shift register to the reset potential,
wherein the second output sub-circuit comprises:
a first output switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the second input terminal, the output terminal, and an operating potential terminal of the shift register, respectively;
a first pull-down switching element, a control terminal, a first terminal, and a second terminal of which are to the second input terminal, a reset potential terminal, and the pull-up node of the shift register, respectively; and
a second pull-down switching component, a control terminal, a first terminal, and a second terminal of which are coupled to the second input terminal, the reset potential terminal, and the pull-down node of the shift register, respectively.
8. A driving method for the gate driving circuit according to claim 7 , comprising: during the period other than the duration in which the one frame of picture is displayed,
supplying the second input signal to second input terminals of all the shift registers in the gate driving circuit, and
outputting, by each of all the shift registers, a second gate driving signal at its output terminal within said period in response to the second input signal received via its second input terminal.
9. The gate driving circuit according to claim 7 , wherein the pull-up sub-circuit comprises:
a first pull-up switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the first input terminal, a second clock signal terminal, and the pull-up node of the shift register, respectively.
10. The gate driving circuit according to claim 9 , wherein the pull-up sub-circuit further comprises:
a second pull-up switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the first input terminal, the reset potential terminal, and the pull-down node of the shift register, respectively.
11. The shift register according to claim 7 , wherein the first output sub-circuit comprises:
a second output switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the pull-up node, the first clock signal terminal, and the output terminal of the shift register, respectively; and
a capacitor connected between the pull-up node and the output terminal.
12. The gate driving circuit according to claim 7 , wherein the reset sub-circuit comprises:
a first reset switching element, a control terminal, a first terminal, and a second terminal of which are coupled to the reset terminal, the reset potential terminal, and the pull-up node of the shift register, respectively;
a second reset switching element, a control terminal, a first terminal and a second terminal of which are coupled to the pull-down node, the reset potential terminal and the output terminal of the shift register, respectively; and
a third reset switching element, a control terminal, a first terminal and a second terminal of which are coupled to the reset terminal, the operating potential terminal and the pull-down node of the shift register, respectively.