IP Library › Granted Patent US 11,156,788
Granted Patent B2
US 11,156,788 · App. 16/317,796 · Granted Oct 26, 2021

Semiconductor package with embedded optical die

Inventors: Vivek Raghunathan (Tempe, AZ); Myung Jin Yim (San Jose, CA)
Assignee: Intel Corporation
G02B6/4206G02B6/122G02B6/132G02B6/42G02B6/428G02B6/4212G02B6/4225H01L25/167
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Quick Facts
Patent No.
US 11,156,788
App. No.
16/317,796
Granted
Oct 26, 2021
Kind
B2
Abstract

Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.

Claims (17)

1. A semiconductor package, comprising:

a first interconnect layer;

an optical die disposed over the first interconnect layer;

a second interconnect layer disposed over the optical die, wherein the second interconnect layer includes at least one metal trace electrically coupled to the optical die;

one or more solder bumps deposited on top of the optical die;

a waveguide coupled to the optical die; and

an optical fiber coupled to the waveguide, wherein the optical fiber is attached to the first interconnect layer using an epoxy, and wherein direct optical fiber coupling to the optical die is avoided by not surface mounting the optical die.

2. The semiconductor package of claim 1 , wherein the second interconnect layer overlies the waveguide.

3. The semiconductor package of claim 1 , wherein the waveguide comprises a bottom cladding layer, a core layer, and a top cladding layer.

4. The semiconductor package of claim 3 , wherein the optical die comprises an edge emitting laser, wherein the edge emitting laser is aligned with the core layer.

5. The semiconductor package of claim 1 , further comprising a third interconnect layer disposed over the first interconnect layer and underlying the second interconnect layer.

6. The semiconductor package of claim 5 , wherein the optical die is disposed overlying a first portion of the first interconnect layer and the third interconnect layer is disposed overlying a second portion of the first interconnect layer, wherein the third interconnect layer is not disposed on the first portion of the first interconnect layer.

7. The semiconductor package of claim 1 , wherein the second interconnect layer includes a dielectric material and wherein the optical die is encapsulated by the dielectric material.

8. The semiconductor package of claim 1 , wherein the epoxy overlies a first portion of the first interconnect layer and the second interconnect layer overlies a second portion of the first interconnect layer, wherein the second interconnect layer does not overlie the second portion of the first interconnect layer.

9. The semiconductor package of claim 1 , further comprising at least one electronic component, wherein the at least one electronic component is electrically coupled to the optical die via the second interconnect layer.

10. The semiconductor package of claim 1 , wherein the epoxy comprises at least one of: (i) an optical epoxy, or (ii) a B-stage epoxy.

11. The semiconductor package of claim 1 , further comprising one or more package-to-board interconnects.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2019
From: YIM, MYUNG JIN; RAGHUNATHAN, VIVEK
To: INTEL CORPORATION
Reel/Frame 050378/0160 →
Continuity (1)
Related Publication 20190302379A1 · Oct 3, 2019