IP Library Granted Patent US 10,839,752
Granted Patent B2
US 10,839,752 · App. 16/323,616 · Granted Nov 17, 2020

Display device and electronic apparatus

Inventors: Takuma Fujii (Kanagawa, JP); Naobumi Toyomura (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
G09G3/3266H01L27/3262H01L27/3265H01L27/3276H01L51/5036G09G3/3233G09G2300/0426G09G2320/0233
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Quick Facts
Patent No.
US 10,839,752
App. No.
16/323,616
Granted
Nov 17, 2020
Kind
B2
Abstract

[Object] It is possible to further improve reliability. [Solution] There is provided a display device including: a pixel unit which is configured with a plurality of pixel circuits arranged in a matrix, each of the pixel circuits including a light emitting element and a driving circuit for driving the light emitting element; scanning lines which are interconnections connected to the respective pixel circuits and are provided to extend in a first direction and correspond to respective rows of a plurality of the pixel circuits; and signal lines which are interconnections connected to the respective pixel circuits and are provided to extend in a second direction orthogonal to the first direction and correspond to respective columns of a plurality of the pixel circuits. One of the scanning lines and the signal lines, provided for the one pixel circuit, which is larger in number is positioned in a lower-level interconnection layer. An electrode of a capacitance element included in the driving circuit is positioned in the interconnection layer in which either the scanning lines or the signal lines are provided.

Claims (37)

1. A display device comprising:

a plurality of pixel circuits arranged in a matrix having a row direction and a column direction, each of the pixel circuits including a light emitting element and a driving circuit for driving the light emitting element, the driving circuit including a capacitive element;

scanning lines connected to the respective pixel circuits and extending in the row direction; and

signal lines connected to the respective pixel circuits and extending in the column direction,

wherein for at least one of the pixel circuits, the number of scanning lines is larger than the number signal lines,

at least one of the scanning lines is located in a first interconnection layer,

at least one of the signal lines is located in a second interconnection layer, the first interconnection layer being located lower than the second interconnection layer in a cross section perspective, and

a first electrode of the capacitance element is located in the second interconnection layer.

2. The display device according to claim 1 ,

wherein the driving circuit includes a plurality of transistors, and

the first and second interconnection layers are stacked on a diffusion layer in which the plurality of transistors are formed.

3. The display device according to claim 2 ,

wherein the light emitting element is an organic light emitting diode, and

the organic light emitting diode is positioned on another interconnection layer of an uppermost layer.

4. The display device according to claim 1 ,

wherein said at least one of the pixel circuits includes the four sub-pixels.

5. The display device according to claim 1 ,

wherein all of the scanning lines are positioned in the first interconnection layer and all of the signal lines are positioned in the second interconnection layer.

6. The display device according to claim 1 ,

wherein the scanning lines are respectively disposed in a plurality of different interconnection layers or the signal lines are respectively disposed in a plurality of different interconnection layers.

7. The display device according to claim 1 , wherein a second electrode of the capacitance element is located in a third interconnection layer that is located higher than the second interconnection layer in the cross section perspective.

8. An electronic apparatus comprising:

a display device which performs display on a basis of a video signal,

wherein the display device includes

a plurality of pixel circuits arranged in a matrix having a row direction and a column direction, each of the pixel circuits including a light emitting element and a driving circuit for driving the light emitting element, the driving circuit including a capacitive element;

scanning lines connected to the respective pixel circuits and extending in the row direction; and

signal lines connected to the respective pixel circuits and extending in the column direction,

wherein for at least one of the pixel circuits, the number of scanning lines is larger than the number of signal lines,

at least one of the scanning lines is located in a first interconnection layer,

at least one of the signal lines is located in a second interconnection layer, the first interconnection layer being located lower than the second interconnection layer in a cross section perspective, and

a first electrode of the capacitance element is located in the second interconnection layer.

9. The electronic apparatus according to claim 8 , wherein the driving circuit includes a plurality of transistors, and the first and second interconnection layers are stacked on a diffusion layer in which the plurality of transistors are formed.

10. The electronic apparatus according to claim 9 , wherein the light emitting element is an organic light emitting diode, and the organic light emitting diode is positioned on another interconnection layer of an uppermost layer.

11. The electronic apparatus according to claim 8 , wherein said at least one of the pixel circuits includes the four sub-pixels.

12. The electronic apparatus according to claim 8 , wherein all of the scanning lines are positioned in the first interconnection layer and all of the signal lines are positioned in the second interconnection layer.

13. The electronic apparatus according to claim 8 , wherein the scanning lines are respectively disposed in a plurality of different interconnection layers or the signal lines are respectively disposed in a plurality of different interconnection layers.

14. The electronic apparatus according to claim 8 , wherein a second electrode of the capacitance element is located in a third interconnection layer that is located higher than the second interconnection layer in the cross section perspective.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2019
From: FUJII, TAKUMA; TOYOMURA, NAOBUMI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 048273/0411 →
Priority Claims (1)
JP 2016-184280 · Sep 21, 2016 · national
Continuity (1)
Related Publication 20190180692A1 · Jun 13, 2019
Cited By (1)
US 12,389,757