Solid-state imaging apparatus, method for driving solid-state imaging apparatus, and electronic equipment
The present disclosure relates to a solid-state imaging apparatus, a method for driving the solid-state imaging apparatus, and electronic equipment for improving the determination speed of comparators and allowing the comparators to operate faster. A differential input circuit operates on a first power supply voltage and outputs a signal when a voltage of a pixel signal is higher than a voltage of a reference signal. A voltage conversion circuit converts the output signal from the differential input circuit into a signal corresponding to a second power supply voltage. A positive feedback circuit accelerates a transition rate at which a comparison result signal of a comparison in voltage between the pixel signal and the reference signal is inverted. Multiple time code transfer sections each include a shift register that transfer a time code. The present disclosure can be applied, for example, to an imaging apparatus including A/D converters disposed in pixels.
1. A solid-state imaging apparatus comprising:
an analog-digital (“A/D”) convertor including:
a differential input circuit configured to operate on a first power supply voltage and to output a signal when a voltage of a pixel signal is higher than a voltage of a reference signal,
a positive feedback circuit configured to operate on a second power supply voltage lower than the first power supply voltage and to accelerate a transition rate at which a comparison result signal indicative of a result of a comparison in voltage between the pixel signal and the reference signal is inverted on a basis of the signal output from the differential input circuit,
a voltage conversion circuit configured to convert the signal output from the differential input circuit into a signal corresponding to the second power supply voltage, and
a data storage section configured to store a time code at a time the comparison result signal is inverted; and
a plurality of time code transfer sections, wherein each of time code transfer section includes:
a shift register configured to transfer the time code,
a write time code transfer section configured to transfer the time code to the data storage section, and
a read time code transfer section configured to transfer the time code from the data storage section.
2. The solid-state imaging apparatus according to claim 1 , wherein each read time code transfer section includes a P-phase time code transfer section configured to transfer the time code for use with P-phase data read from the data storage section and a D-phase time code transfer section configured to transfer the time code for use with D-phase data read from the data storage section.
3. The solid-state imaging apparatus according to claim 2 , wherein:
the data storage section includes a P-phase data storage section configured to store the time code for use with P-phase data and a D-phase data storage section configured to store the time code for use with D-phase data;
the P-phase time code transfer section transfers the time code for use with P-phase data written in the P-phase data storage section; and
the D-phase time code transfer section transfers the time code for use with D-phase data written in the D-phase data storage section.
4. The solid-state imaging apparatus according to claim 3 , wherein the P-phase time code transfer section transfers the time code for use with P-phase data written in the P-phase data storage section at a same timing as that of the D-phase time code transfer section transferring the time code for use with D-phase data.
5. The solid-state imaging apparatus according to claim 3 , wherein the P-phase time code transfer section executes shift clock on the shift registers in a manner complementary to the D-phase time code transfer section executing shift clock on the shift registers.
6. The solid-state imaging apparatus according to claim 1 , wherein the read time code transfer section alternately transfers the time code for use with P-phase data and the time code for use with D-phase data.
7. The solid-state imaging apparatus according to claim 1 , wherein each time code transfer section includes a P-phase time code transfer configured to transfer the time code for use with P-phase data and a D-phase time code transfer section configured to transfer the time code for use with D-phase data.
8. The solid-state imaging apparatus according to claim 1 , wherein the data storage section includes a write data storage section configured to store the time code supplied from the write time code transfer section, and a read data storage section configured to store the time code to be supplied to the read time code transfer section.
9. The solid-state imaging apparatus according to claim 1 , wherein the data storage section includes a write data storage section configured to store the time code supplied from the write time code transfer section, a P-phase data storage section configured to store the time code for use with P-phase data, and a D-phase data storage section configured to store the time code for use with D-phase data.
10. The solid-state imaging apparatus according to claim 1 , wherein the data storage section includes a P-phase data storage section configured to store the time code for use with P-phase data and a D-phase data storage section configured to store the time code for use with D-phase data.
11. The solid-state imaging apparatus according to claim 10 , further comprising:
a bidirectional buffer configured to switch a write operation and a read operation of the time code on the data storage section.
12. The solid-state imaging apparatus according to claim 1 , wherein each shift register includes a plurality of D-F/Fs each brought into a high-impedance state when an input clock signal has a predetermined value.
13. The solid-state imaging apparatus according to claim 1 , wherein the A/D converter is shared by a plurality of pixels.
14. The solid-state imaging apparatus according to claim 13 , wherein the A/D converter is arranged for each pixel.
15. The solid-state imaging apparatus according to claim 1 , further comprising:
a plurality of semiconductor substrates.
16. A method for driving a solid-state imaging apparatus comprising:
an analog-digital (“A/D”) converter including:
a differential input circuit configured to operate on a first power supply voltage,
a positive feedback circuit configured to operate on a second power supply voltage lower than the first power supply voltage,
a comparator having a voltage conversion circuit, and
a data storage section, and
a plurality of time code transfer sections each including a shift register,
the method comprising:
causing the differential input circuit to output a signal when a voltage of a pixel signal is higher than a voltage of a reference signal;
causing the voltage conversion circuit to convert the signal output from the differential input circuit into a signal corresponding to the second power supply voltage;
causing the positive feedback circuit to accelerate a transition rate at which a comparison result signal indicative of a result of a comparison in voltage between the pixel signal and the reference signal is inverted, inverted on a basis of the signal output by the differential input circuit converted by the voltage conversion circuit;
causing the data storage section to store a time code at a time the comparison result signal is inverted; and
causing each of the plurality of time code transfer sections to transfer the time code, wherein each time code transfer section includes:
a shift register configured to transfer the time code,
a write time code transfer section configured to transfer the time code to the data storage section, and
a read time code transfer section configured to transfer the time code from the data storage section.
17. Electronic equipment comprising:
a solid-state imaging apparatus comprising:
an analog-digital (“A/D”) convertor including:
a differential input circuit configured to operate on a first power supply voltage and to output a signal when a voltage of a pixel signal is higher than a voltage of a reference signal,
a positive feedback circuit configured to operate on a second power supply voltage lower than the first power supply voltage and to accelerate a transition rate at which a comparison result signal indicative of a result of a comparison in voltage between the pixel signal and the reference signal is inverted on a basis of the signal output from the differential input circuit,
a voltage conversion circuit configured to convert the output signal output from the differential input circuit into a signal corresponding to the second power supply voltage, and
a data storage section configured to store a time code at a time the comparison result signal is inverted, and
a plurality of time code transfer sections, wherein each time code transfer includes:
a shift register configured to transfer the time code
a write time code transfer section configured to transfer the time code to the data storage section, and
a read time code transfer section configured to transfer the time code from the data storage section.
18. The electronic equipment of claim 17 , wherein each read time code transfer section includes a P-phase time code transfer section configured to transfer the time code for use with P-phase data read from the data storage section.
19. The electronic equipment of claim 18 , wherein each read time code transfer section further includes a D-phase time code transfer section configured to transfer the time code for use with D-phase data read from the data storage section.
20. The electronic equipment of claim 19 , wherein the data storage section includes a P-phase data storage section configured to store the time code for use with P-phase data and a D-phase data storage section configured to store the time code for use with D-phase data.