IP Library Granted Patent US 10,797,181
Granted Patent B2
US 10,797,181 · App. 16/327,969 · Granted Oct 6, 2020

Semiconductor device and method for manufacturing the same

Inventors: Tomoyoshi Mishima (Tokyo, JP); Fumimasa Horikiri (Ibaraki, JP)
Assignees: HOSEI UNIVERSITY; SCIOCS COMPANY LIMITED; SUMITOMO CHEMICAL COMPANY, LIMITED
H01L29/872C23C16/34H01L21/20H01L21/205H01L29/06H01L29/2003H01L29/47H01L29/66136H01L29/66143H01L29/861H01L29/868H01L29/8613H01L33/32
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Quick Facts
Patent No.
US 10,797,181
App. No.
16/327,969
Granted
Oct 6, 2020
Kind
B2
Abstract

A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×10 20 cm −3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.

Claims (37)

1. A semiconductor device that functions as a pn-junction diode, comprising:

a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor;

a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer, and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of more than 1−10 20 cm −3 ;

a first electrode disposed in contact with the first semiconductor layer; and

a second electrode disposed in contact with the second semiconductor layer,

wherein a thickness of the second semiconductor layer is less than 100 nm, and

the second semiconductor layer is only a single semiconductor layer with p-type conductivity in the semiconductor device.

2. The semiconductor device according to claim 1 , wherein a positive hole concentration in the second semiconductor layer is 1×10 16 cm −3 or more.

3. The semiconductor device according to claim 1 , wherein a breakdown voltage is 400 V or more when a reverse voltage is applied.

4. The semiconductor device according to claim 1 , wherein the second electrode is disposed in contact with the second semiconductor layer and not in contact with the first semiconductor layer.

5. The semiconductor device according to claim 1 , wherein

the second electrode is disposed in contact with the second semiconductor layer and the first semiconductor layer; and

the semiconductor device is a Junction Barrier Schottky diode that functions as the pn-junction diode and functions as a Schottky barrier diode.

6. The semiconductor device according to claim 5 , wherein in a planar view, a proportion of an area where the second electrode is in contact with the second semiconductor layer, based on the sum of an area where the second electrode is in contact with the second semiconductor layer and an area where the second electrode is in contact with the first semiconductor layer, is 20% or more.

7. The semiconductor device according to claim 1 ,

wherein the second semiconductor layer comprises the p-type impurity at a concentration of 2×10 20 cm −3 or more.

8. A method for manufacturing a semiconductor device that functions as a pn-junction diode, comprising:

preparing a semiconductor laminate including a first semiconductor layer with n-type conductivity, which contains a gallium nitride-based semiconductor, and a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of more than 1−10 20 cm −3 ;

forming a first electrode disposed in contact with the first semiconductor layer; and

forming a second electrode disposed in contact with the second semiconductor layer,

wherein a thickness of the second semiconductor layer is less than 100 nm, and

the second semiconductor layer is only a single semiconductor layer with p-type conductivity in the semiconductor device.

9. The method for manufacturing a semiconductor device according to claim 8 , further comprising removing partially an entire thickness of the semiconductor layer by a wet etching, and exposing the first semiconductor layer,

wherein forming the second electrode is forming the second electrode so as to have a shape extending from a surface of the second semiconductor layer to a surface of the first semiconductor layer which is exposed by the wet etching, and thereby forming the second electrode disposed in contact with the second semiconductor layer and the first semiconductor layer, and

a Junction Barrier Schottky diode that functions as the pn-junction diode and functions as a Schottky Barrier diode is manufactured as the semiconductor device.

10. The method for manufacturing a semiconductor device according to claim 9 , wherein an anodization is used as the wet etching.

11. The method according to claim 8 ,

wherein the second semiconductor layer comprises the p-type impurity at a concentration of 2×10 20 cm −3 or more.

12. A semiconductor laminate capable of functioning as a pn-junction diode, comprising:

a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor; and

a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer, and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of more than 1×10 20 cm −3 ,

wherein a thickness of the second semiconductor layer is less than 100 nm, and

the second semiconductor layer is only a single semiconductor layer with p-type conductivity in the semiconductor laminate.

13. The semiconductor laminate according to claim 12 , wherein an upper surface of the second semiconductor layer is prepared as a contact area of an electrode.

14. The semiconductor laminate according to claim 12 , wherein an upper surface of the second semiconductor layer is an upper surface of the semiconductor laminate.

15. The semiconductor laminate according to claim 12 ,

wherein the second semiconductor layer comprises the p-type impurity at a concentration of 2×10 20 cm −3 or more.

Assignments (2)
MERGER Recorded Dec 16, 2022
From: SCIOCS COMPANY LIMITED
To: SUMITOMO CHEMICAL COMPANY LIMITED
Reel/Frame 062142/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2019
From: MISHIMA, TOMOYOSHI; HORIKIRI, FUMIMASA
To: HOSEI UNIVERSITY; SCIOCS COMPANY LIMITED; SUMITOMO CHEMICAL COMPANY, LIMITED
Reel/Frame 050747/0703 →
Priority Claims (1)
JP 2016-166155 · Aug 26, 2016 · national
Continuity (1)
Related Publication 20190189808A1 · Jun 20, 2019