Structure, method for manufacturing same, semiconductor element, and electronic circuit

1. A structure, comprising:

a metal oxide semiconductor layer; and

a noble metal oxide layer,

wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other;

wherein the metal oxide in the metal oxide semiconductor layer comprises an oxide of one or more metal elements selected from the group consisting of In, Sn, Cd, Zn, Ga, and Ge, provided that the metal oxide is not a zinc oxide; and

a film thickness of the noble metal oxide layer is more than 10 nm.

2. The structure according to claim 1 , comprising a depletion region.

3. The structure according to claim 1 , wherein the noble metal oxide layer comprises a polycrystalline structure.

4. The structure according to claim 1 , further comprising a noble metal layer adjacent to the noble metal oxide layer and on a side opposite to the metal oxide semiconductor layer.

5. The structure according to claim 4 , further comprising a low-resistance base metal layer adjacent to the noble metal layer and on a side opposite to the noble metal oxide layer.

6. The structure according to claim 1 , wherein noble metal oxide in the noble metal oxide layer is one or more selected from the group consisting of palladium oxide, ruthenium oxide, platinum oxide, iridium oxide, silver oxide, rhenium oxide, osmium oxide, rhodium oxide, nickel oxide, and gold oxide.

7. The structure according to claim 1 , wherein noble metal oxide in the noble metal oxide layer is one or more selected from the group consisting of PdO having a PdO structure, RuO 2 having a rutile structure, PtO 2 having an α-PtO 2 structure, IrO 2 having a rutile structure, Ag 2 O having a Cu 2 O structure, ReO 3 having a skutterudite structure, OsO 2 having a rutile structure, Rh 2 O 3 having a corundum structure, NiO having a NiO structure, and Au 2 O 3 having a Au 2 O 3 structure.

8. The structure according to claim 1 , wherein an average crystalline particle diameter of noble metal oxide in the noble metal oxide layer is equal to or less than a film thickness of the noble metal oxide layer.

9. The structure according to claim 1 , wherein interface roughness of the noble metal oxide layer is 5 nm or less.

10. The structure according to claim 1 , wherein a carbon concentration in a Schottky interface between the metal oxide semiconductor layer and the noble metal oxide layer is 2×10 19 cm −3 or less.

11. The structure according to claim 1 , wherein resistivity of the noble metal oxide layer is 1×10 −2 Ω·cm or less.

12. The structure according to claim 1 , wherein a work function of noble metal oxide in the noble metal oxide layer is 4.8 eV or more.

13. The structure according to claim 1 , wherein the metal oxide semiconductor layer is amorphous or polycrystalline.

14. The structure according to claim 1 , wherein a content ratio of Ga or In in the metal oxide semiconductor layer is 45 atomic % or more based on total metal elements in the metal oxide semiconductor layer.

15. The structure according to claim 1 , wherein the metal oxide semiconductor layer is randomly oriented.

16. The structure according to claim 1 , wherein a Schottky barrier height between the noble metal oxide layer and the metal oxide semiconductor layer is 0.7 eV or more.

17. The structure according to claim 1 , further comprising a substrate on a side of the noble metal oxide layer and opposite to the metal oxide semiconductor layer.

18. The structure according to claim 1 , further comprising an ohmic electrode layer, wherein the ohmic electrode layer and the noble metal oxide layer are not in contact with each other.

19. The structure according to claim 1 , wherein the metal oxide semiconductor layer is formed in one layer, or two or more layers, and any one layer of the metal oxide semiconductor layer is adjacent to the noble metal oxide layer when the metal oxide semiconductor layer is formed in two or more layers.

20. The structure according to claim 1 , wherein withstand voltage when reverse voltage is applied is 0.5 MV/cm or more.

21. The structure according to claim 1 , wherein current density is 1×10 −6 A/cm 2 or less when reverse bias of 0.2 MV/cm is applied.

22. The structure according to claim 1 , wherein an ideality factor of a diode when forward bias is applied is 1.5 or less.

23. The structure according to claim 1 , wherein current density reaches 1000 A/cm 2 at forward bias of 5 V or less.

24. A method for manufacturing a structure, wherein the metal oxide semiconductor layer is formed by sputtering in an atmosphere into which hydrogen or water is introduced to obtain the structure according to claim 1 .

25. A method for manufacturing the structure, wherein a film of the noble metal oxide layer is formed by sputtering in an atmosphere in which 50% or more of a flow rate of an introduced gas is oxygen to obtain the structure according to claim 1 .

26. The method for manufacturing the structure according to claim 24 , wherein annealing is performed at 220 to 500° C. after the noble metal oxide layer and the metal oxide semiconductor layer are formed.

27. The method for manufacturing the structure according to claim 24 ,

wherein the noble metal oxide layer and the metal oxide semiconductor layer are continuously formed by sputtering, or

wherein vacuum or an inert atmosphere is provided between formation of the noble metal oxide layer and formation of the metal oxide semiconductor layer.

28. A semiconductor element comprising the structure according to claim 1 .

29. The semiconductor element according to claim 28 , which is a power semiconductor element, a diode element, a Schottky barrier diode element, an electrostatic discharge protection diode, a transient voltage protection diode, a light-emitting diode, a metal-semiconductor field-effect transistor, a junction field-effect transistor, a metal-oxide semiconductor field-effect transistor, a Schottky source/drain metal-oxide semiconductor field-effect transistor, an avalanche multiplication photoelectric conversion element, a solid state imaging element, or a solar cell element, an optical sensor element, a touch-sensor element, a display element, or resistive random access memory.

30. An electronic circuit comprising the semiconductor element according to claim 28 .

31. An electrical apparatus, an electronic apparatus, a vehicle, or a power engine, comprising the electronic circuit according to claim 30 .