Array substrate and method for manufacturing the same, and display device

1. An array substrate comprising:

a substrate having a display region and a peripheral region surrounding the display region, the display region having a plurality of pixels arranged in an array, and each of the plurality of pixels comprising a light transmission region and a light shielding region; and

a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels,

wherein a ratio of an area of the light shielding block to an area of the at least one pixel close to the peripheral region is set as one of N values constituting an arithmetic progression, wherein 3≤N≤101, and wherein the arithmetic progression has a first item of 0 and a last item of 100%.

2. The array substrate according to claim 1 , further comprising a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer on the substrate, and the array substrate further comprising a light shielding layer located between the active layer and the substrate, wherein the light shielding block is disposed on a same layer as the light shielding layer.

3. The array substrate according to claim 1 , further comprising a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer, a gate electrode, and a gate dielectric layer therebetween, wherein the light shielding block is disposed on a same layer as the gate electrode.

4. The array substrate according to claim 1 , wherein the display region has a non-rectangular shape.

5. The array substrate according to claim 1 , further comprising a thin film transistor located on the substrate and in the light shielding region, the thin film transistor comprising an active layer, a gate electrode, a gate dielectric layer therebetween, and a source/drain electrode disposed on the active layer, wherein the light shielding block is disposed on a same layer as the source/drain electrode.

6. The array substrate according to claim 1 , wherein the light shielding block comprises a first portion and a second portion respectively covering opposite ends of the light transmission region of the at least one pixel close to the peripheral region.

7. The array substrate according to claim 6 , wherein the light shielding block further comprises a third portion located between the first portion and the second portion.

8. The array substrate according to claim 1 , wherein an absolute value of a difference between the one of the N values and a desired set value depending on a shape of an edge of the display region is smaller than an absolute value of a difference between any other one of the N values and the desired set value.

9. A display device comprising the array substrate according to claim 1 .

10. A method for manufacturing an array substrate, the method comprising:

providing a substrate having a display region and a peripheral region surrounding the display region, the display region having a plurality of pixels arranged in an array, and each of the plurality of pixels comprising a light transmission region and a light shielding region; and

forming a light shielding block to cover at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels,

wherein a ratio of an area of the light shielding block to an area of the at least one pixel close to the peripheral region is set as one of N values constituting an arithmetic progression, wherein 3≤N≤101, and wherein the arithmetic progression has a first item of 0 and a last item of 100%.

11. The method according to claim 10 , further comprising forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises:

forming a light shielding material layer on the substrate;

patterning the light shielding material layer to form a light shielding layer in the light shielding region, and to form the light shielding block;

forming a first insulating layer on the light shielding layer and the light shielding block;

forming an active layer in the light shielding region and on the first insulating layer;

forming a second insulating layer as a gate dielectric layer on the active layer; and

forming a gate electrode in the light shielding region and on the second insulating layer.

12. The method according to claim 10 , further comprising forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises:

forming an active layer on the substrate and in the light shielding region;

forming a third insulating layer as a gate dielectric layer on the active layer;

forming a first conductive layer on the third insulating layer; and

patterning the first conductive layer to form a gate electrode in the light shielding region, and to form the light shielding block.

13. The method according to claim 12 , further comprising, before forming the active layer, forming a light shielding layer on the substrate and in the light shielding region, and forming a fourth insulating layer on the light shielding layer.

14. The method according to claim 10 , further comprising forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises:

forming a second conductive layer on the substrate;

patterning the second conductive layer to form a gate electrode in the light shielding region, and to form the light shielding block;

forming a fourth insulating layer on the gate electrode and the light shielding block; and

forming an active layer in the light shielding region and on the fourth insulating layer.

15. The method according to claim 10 , further comprising forming a thin film transistor on the substrate and in the light shielding region, wherein forming the thin film transistor comprises:

forming a third conductive layer on the substrate;

patterning the third conductive layer to form a gate electrode in the light shielding region;

forming a fifth insulating layer as a gate dielectric layer on the gate electrode;

forming an active layer in the light shielding region and on the fifth insulating layer;

forming a fourth conductive material layer on the active layer; and

patterning the fourth conductive material layer to form a source/drain electrode in the light shielding region, and form the light shielding block.

16. The method according to claim 10 , wherein forming the light shielding block in the light transmission region of the at least one pixel close to the peripheral region comprises forming a first portion and a second portion respectively covering opposite ends of the light transmission region of the at least one pixel close to the peripheral region.

17. The method according to claim 16 , wherein a third portion located between the first portion and the second portion is further formed.

18. The method according to claim 10 , wherein an absolute value of a difference between the one of the N values and a desired set value depending on a shape of an edge of the display region is smaller than an absolute value of a difference between any other one of the N values and the desired set value.