RRAM process integration scheme and cell structure with reduced masking operations
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.
1. A resistive random access memory (RRAM) comprising:
one or more bottom electrodes comprised of tungsten;
one or more switching layers comprised of hafnium oxide disposed above the bottom electrode, the switching layer comprising a switchable filament;
one or more resistive layers disposed above the switching layer;
one or more bit lines disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more RRAM cells along the bit line; and
further comprising a via disposed below the switching layer, wherein the via is directly in contact with the switching layer; wherein the via is comprised of tungsten.
2. The RRAM of claim 1 , wherein the one or more resistive layers are comprised of a conductive metal oxide.
3. The RRAM of claim 1 , wherein the one or more bottom electrodes comprise a word line that is orthogonal to the bit line.
4. The RRAM of claim 3 , further comprising:
one or more non-linear device layers disposed below the bit line and above the resistive layer.
5. The RRAM of claim 3 , further comprising:
one or more non-linear device layers disposed above the word line and below the switching layer.
6. The RRAM of claim 5 , wherein the one or more non-linear device layers comprise a metal-insulator-metal structure.
7. A resistive random access memory (RRAM) comprising:
a switching layer;
a resistive layer disposed above the switching layer, wherein the resistive layer extends laterally to connect two or more memory cells along a bit line;
a top electrode disposed above the resistive layer and
further comprising a via disposed below the switching layer, wherein the via is directly in contact with the switching layer; wherein the via is comprised of tungsten.
8. The RRAM of claim 7 , further comprising a bottom electrode disposed below the switching layer.
9. The RRAM of claim 7 , wherein a material of the switching layer comprises a transition metal oxide.
10. The RRAM of claim 7 , wherein a material of the switching layer comprises tantalum oxide.
11. The RRAM of claim 7 , wherein a material of the switching layer comprises titanium oxide.
12. The RRAM of claim 7 , wherein a material of the switching layer comprises hafnium oxide.
13. The RRAM of claim 7 , wherein the top electrode corresponds to a standard metallization layer used for connections on a semiconductor device.
14. The RRAM of claim 7 , wherein the switching layer has a resistance that changes upon application of a voltage.