Forming method of epitaxial layer, forming method of 3D NAND memory and annealing apparatus
A forming method of an epitaxial layer, a forming method of a 3D NAND memory and an annealing apparatus are provided. In the forming method of the epitaxial layer, a first annealing process is performed for eliminating a stress generated in a stacked structure. When performing the first annealing process, a silicon-containing mixture is formed on a sidewall and a bottom surface of a trench. Thus, after performing the first annealing process, a second annealing process is performed for removing the silicon-containing mixture disposed at the sidewall and the bottom surface of the trench, such that when subsequently forming the epitaxial layer, a growth interface of the epitaxial layer is a pure substrate material interface, so as to prevent from be formed a void defect in the epitaxial layer formed in the trench.
1. A forming method of an epitaxial layer, comprising:
providing a substrate, wherein a stacked structure having a plurality of first insulating layers and a plurality of second insulating layers stacked alternately is formed on the substrate;
etching the stacked structure to form a plurality of channel holes passing through the stacked structure;
etching the substrate situated at bottoms of the plurality of channel holes along the plurality of channel holes to form a plurality of trenches in the substrate;
performing a first annealing process after forming the plurality of trenches, wherein a silicon-containing mixture is formed on sidewalls and bottom surfaces of the plurality of trenches when performing the first annealing process;
performing a second annealing process after performing the first annealing process, so as to remove the silicon-containing mixture; and
utilizing a selective epitaxial growth process to form an epitaxial layer in the plurality of trenches after performing the second annealing process, wherein the plurality of trenches are fully filled with the epitaxial layer.
2. The forming method of the epitaxial layer of claim 1 , wherein in addition to comprising the silicon in the silicon-containing mixture, the silicon-containing mixture further comprises one or more of elements contained in a gas used for the first annealing process, elements contained in a source gas and/or a by-product when forming the plurality of first insulating layers, and elements contained in a source gas and/or a by-product when forming the plurality of second insulating layers.
3. The forming method of the epitaxial layer of claim 1 , wherein a gas atmosphere of the first annealing process is N 2 , and a gas atmosphere of the second annealing process is H 2 .
4. The forming method of the epitaxial layer of claim 1 , wherein a material of the plurality of first insulating layers and a material of the plurality of second insulating layers are individually one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride, and the material of the plurality of first insulating layers is different from the material of the plurality of second insulating layers.
5. The forming method of the epitaxial layer of claim 4 , wherein in addition to comprising the silicon in the silicon-containing mixture, the silicon-containing mixture further comprises one or more of N, C, H, and O.
6. The forming method of the epitaxial layer of claim 1 , wherein during the second annealing process, a temperature is 800-1200° C., a process time is 1-10 hours and a pressure of a chamber is less than 100 torr.
7. The forming method of the epitaxial layer of claim 1 , wherein a gas utilized in the second annealing process is reacted with the silicon-containing mixture to form a gaseous reactant when performing the second annealing process.
8. The forming method of the epitaxial layer of claim 1 , wherein Miller indices of the sidewall of the plurality of trenches are expressed as (111) after performing the second annealing process.
9. A forming method of a 3D NAND memory, comprising:
providing a substrate, wherein a stacked structure having a plurality of first insulating layers and a plurality of second insulating layers stacked alternately is formed on the substrate;
etching the stacked structure to form a plurality of channel holes passing through the stacked structure;
etching the substrate situated at bottoms of the plurality of channel holes along the plurality of channel holes to form a plurality of trenches in the substrate;
performing a first annealing process after forming the plurality of trenches, wherein a silicon-containing mixture is formed on sidewalls and bottom surfaces of the plurality of trenches when performing the first annealing process;
performing a second annealing process after performing the first annealing process, so as to remove the silicon-containing mixture;
utilizing a selective epitaxial growth process to form an epitaxial layer in the plurality of trenches after performing the second annealing process, wherein the plurality of trenches are fully filled with the epitaxial layer;
forming a storage structure in the plurality of channel holes above the epitaxial layer; and removing the plurality of first insulating layers, and forming a plurality of metal gates at positions corresponding to the removed plurality of first insulating layers.
10. The forming method of the 3D NAND memory of claim 9 , wherein in addition to comprising the silicon in the silicon-containing mixture, the silicon-containing mixture further comprises one or more of elements contained in a gas used for the first annealing process, elements contained in a source gas and/or a by-product when forming the plurality of first insulating layers, and elements contained in a source gas and/or a by-product when forming the plurality of second insulating layers.
11. The forming method of the 3D NAND memory of claim 9 , wherein a gas atmosphere of the first annealing process is N 2 , a gas atmosphere of the second annealing process is H 2 .
12. The forming method of the 3D NAND memory of claim 9 , wherein a material of the plurality of first insulating layers and a material of the plurality of second insulating layers are individually one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride, and the material of the plurality of first insulating layers is different from the material of the plurality of second insulating layers.
13. The forming method of the epitaxial layer of claim 12 , wherein in addition to comprising the silicon in the silicon-containing mixture, the silicon-containing mixture further comprises one or more of N, C and H.
14. The forming method of the 3D NAND memory of claim 9 , wherein during the second annealing process, a temperature is 800-1200° C., a process time is 1-10 hours and a pressure of a chamber is less than 100 torr.
15. The forming method of the 3D NAND memory of claim 9 , wherein a gas utilized in the second annealing process is reacted with the silicon-containing mixture to form a gaseous reactant when performing the second annealing process.
16. The forming method of the 3D NAND memory of claim 9 , wherein Miller indices of the sidewall of the plurality of trenches are expressed as (111) after performing the second annealing process.