Semiconductor device having gate insulating layer

1. A semiconductor device comprising:

a substrate comprising an upper surface;

a gate trench on the upper surface of the substrate, the gate trench including an upper region and a lower region,

the upper region of the gate trench including a first inner surface,

the lower region of the gate trench including a second inner surface and a lower surface;

an upper gate insulating layer on the first inner surface;

a lower gate insulating layer on the second inner surface and the lower surface, the lower gate insulating layer connected to the upper gate insulating layer;

a first gate barrier layer on a first inner side of the lower gate insulating layer;

a gate electrode on a second inner side of the first gate barrier layer, the gate electrode filling the lower region of the gate trench; and

a gate buried portion on the gate electrode,

wherein a diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.

2. The semiconductor device of claim 1 , wherein a diameter of an outer circumference of the upper end of the lower gate insulating layer is greater than a diameter of an outer circumference of the lower end of the upper gate insulating layer.

3. The semiconductor device of claim 1 , wherein a step is between the first inner side of the upper gate insulating layer and the second inner side of the lower gate insulating layer.

4. The semiconductor device of claim 1 , wherein the gate buried portion includes doped polysilicon.

5. The semiconductor device of claim 1 , wherein a ratio of a height of the lower gate insulating layer to a height of the upper gate insulating layer ranges from 1:0.95 to 1:0.98.

6. The semiconductor device of claim 1 , further comprising:

a second gate barrier layer between the gate buried portion and the gate electrode, the second gate barrier layer covering at least a portion of a lower surface of the gate buried portion.

7. The semiconductor device of claim 6 , wherein,

the gate electrode includes tungsten, and

the second gate barrier layer includes tungsten nitride.

8. The semiconductor device of claim 6 , wherein,

a lower surface of the second gate barrier layer is at a same level as the lower end of the upper gate insulating layer, and

the second gate barrier layer is in contact with an inner wall of the upper gate insulating layer.

9. The semiconductor device of claim 6 , further comprising:

a work function adjusting layer configured to cover a side surface of the gate buried portion,

wherein an upper end of the work function adjusting layer is at the same level as an upper surface of the gate buried portion, and

a lower end of the work function adjusting layer is in contact with the second gate barrier layer.

10. The semiconductor device of claim 6 , wherein,

an upper surface of the second gate barrier layer is at the same level as the upper end of the lower gate insulating layer, and

the second gate barrier layer is in contact with an inner wall of the first gate barrier layer.

11. The semiconductor device of claim 6 , wherein,

the first gate barrier layer includes a protrusion configured to protrude toward an inner side of the gate trench, the protrusion being formed at an upper end of the first gate barrier layer; and

an upper surface of the second gate barrier layer and an upper surface of the protrusion are positioned at the same level in the upper region of the gate trench.

12. The semiconductor device of claim 6 , wherein,

the first gate barrier layer includes a protrusion configured to protrude toward an inner side of the gate trench, the protrusion being formed at an upper end of the first gate barrier layer,

an upper surface of the protrusion is positioned at a same level as the upper end of the lower gate insulating layer, and

an upper surface of the second gate barrier layer is positioned at the same level as the upper surface of the protrusion.

13. A semiconductor device comprising:

a substrate comprising an upper surface;

a gate trench on the upper surface of the substrate, the gate trench including an upper region and a lower region, the upper region including a first inner surface, the lower region including a second inner surface;

an upper gate insulating layer on the first inner surface of the upper region of the gate trench;

a lower gate insulating layer on a) the second inner surface of the lower region of the gate trench and b) a lower surface of the lower region of the gate trench, the lower gate insulating layer connected to the upper gate insulating layer;

a first gate barrier layer on an inner side of the lower gate insulating layer;

a gate electrode on an inner side of the first gate barrier layer, the gate electrode filling the lower region of the gate trench; and

a gate buried portion on the gate electrode,

wherein a diameter of an outer circumference of an upper end of the first gate barrier layer is greater than a diameter of a lower surface of the gate buried portion.

14. The semiconductor device of claim 13 , wherein the gate buried portion includes doped polysilicon.

15. The semiconductor device of claim 13 , further comprising:

a second gate barrier layer between the gate buried portion and the gate electrode, the second gate barrier layer configured to cover at least a portion of the lower surface of the gate buried portion.

16. The semiconductor device of claim 15 , wherein,

a lower surface of the second gate barrier layer is at the same level as a lower end of the upper gate insulating layer, and

the second gate barrier layer is in contact with an inner wall of the upper gate insulating layer.

17. The semiconductor device of claim 15 , wherein,

the first gate barrier layer includes a protrusion configured to protrude toward an inner side of the gate trench, the protrusion being formed at an upper end of the first gate barrier layer,

an upper surface of the protrusion is at the same level as an upper end of the lower gate insulating layer, and

an upper surface of the second gate barrier layer is at the same level as the upper surface of the protrusion.

18. A semiconductor device comprising:

a substrate comprising an active region;

a gate trench configured to extend in one direction on an upper surface of the substrate;

an upper gate insulating layer on an inner surface of an upper region of the gate trench;

a lower gate insulating layer on a) an inner surface of a lower region of the gate trench and b) a lower surface of a lower region of the gate trench, the lower gate insulating layer connected to the upper gate insulating layer;

a first gate barrier layer on an inner side of the lower gate insulating layer;

a gate electrode on an inner side of the first gate barrier layer, the gate electrode configured to fill the lower region of the gate trench;

a second gate barrier layer; and

a gate buried portion, the second gate barrier layer and the gate buried portion being sequentially stacked on the gate electrode,

wherein the upper gate insulating layer and the lower gate insulating layer are in the active region,

an upper end of the first gate barrier layer is positioned at the same level as an upper surface of the gate electrode,

a lower surface of the second gate barrier layer is positioned at the same level as a lower end of the lower gate insulating layer are positioned, and

a diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.

19. The semiconductor device of claim 18 , wherein the gate buried portion includes doped polysilicon.

20. The semiconductor device of claim 18 , further comprising:

a work function adjusting layer covering a side surface of the gate buried portion.