Hybrid return-to-zero voltage-mode DAC driver
View Patent ↗A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).
1. A voltage-mode digital-to-analog converter (DAC), comprising:
multiple bit processing circuits to generate an output voltage responsive to a binary input, each of the multiple bit processing circuits including
a first switch circuit to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d,
a second switch circuit to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and
wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).
2. The voltage-mode DAC according to claim 1 , wherein the first and second switch circuits each comprise push-pull voltage-mode sub-drivers.
3. The voltage-mode DAC according to claim 1 , wherein the scaling value d comprises a selectable value between 0 and 1 such that the first and second output loads cooperate to exhibit hybrid direct driver and split driver characteristics.
4. The voltage-mode DAC according to claim 1 , wherein the first and second switching circuits are sequenced during the first and second bit times in accordance with a return-to-zero protocol.
5. The voltage-mode DAC according to claim 1 , further comprising:
a current-steering output stage coupled to the third output load.
6. The voltage-mode DAC according to claim 5 , wherein the current-steering output stage includes tunable current source/sink circuitry to compensate for common-mode data signals.
7. The voltage-mode DAC according to claim 1 , wherein the first and second switch circuits alternatingly activate during the first and second bit times.
8. A method of operation in a voltage-mode DAC, the method comprising:
operating multiple bit processing circuits to generate an output voltage responsive to a binary input, the operating of each of the multiple bit processing circuits including
selectively coupling one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d,
selectively coupling one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load; and
wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).
9. The method according to claim 8 , wherein the operating is carried out using a return-to-zero protocol.
10. The method according to claim 8 , wherein the selectively coupling to the first and second output loads is carried out in response to alternatingly activating corresponding first and second switch circuits.
11. A voltage-mode driver, comprising:
a first voltage-mode sub-driver to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d,
a second voltage-mode sub-driver to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and
wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d).
12. The voltage-mode driver according to claim 11 , wherein the first and second voltage-mode sub-drivers each comprise push-pull voltage-mode sub-drivers.
13. The voltage-mode DAC according to claim 11 , wherein the scaling value d comprises a selectable value between 0 and 1 such that the first and second output loads cooperate to exhibit hybrid direct driver and split driver characteristics.
14. The voltage-mode DAC according to claim 11 , wherein the first and second switching circuits are sequenced during the first and second bit times in accordance with a return-to-zero protocol.
15. The voltage-mode DAC according to claim 11 , further comprising:
a current-steering output stage coupled to the third output load.
16. The voltage-mode DAC according to claim 15 , wherein the current-steering output stage includes tunable current source/sink circuitry to compensate for common-mode data signals.
17. The voltage-mode DAC according to claim 11 , wherein the first and second switch circuits alternatingly activate during the first and second bit times.