Voltage-mode DAC driver with programmable mode output units

1. A digital-to-analog converter (DAC), comprising:

input circuitry to receive a digital word of N bits;

an array of N bit processing units disposed in parallel;

wherein each of the N bit processing units comprises

first switch circuitry to generate a first output state based on a first value of a received one of the N bits;

second switch circuitry to generate a second output state based on a second value of the received one of the N bits; and

selectively enabled third switch circuitry to generate, when enabled, a conditional third output state and to cooperate with the first switch circuitry and the second switch circuitry to define a tri-state DAC configuration, the first switch circuitry and the second switch circuitry forming a dual-state DAC configuration when the selectively enabled third switch circuitry is disabled.

2. The DAC according to claim 1 , embodied as a voltage-mode DAC.

3. The DAC according to claim 1 , wherein each of the N bit processing units comprises

an output impedance;

respective high, low and intermediate voltage sources;

wherein the first switch circuitry includes a first switch to couple the output impedance to the high voltage source based on the first value of the received one of the N input bits;

wherein the second switch circuitry includes a second switch to couple the output impedance to the low voltage source based on the second value of the received one of the N input bits; and

wherein the third switch circuitry includes a third switch responsive to control circuitry to conditionally couple the output impedance to the intermediate voltage source.

4. The DAC according to claim 3 , wherein the control circuitry independently enables/disables the third switch circuitry of each of the N bit processing units.

5. The DAC according to claim 3 , wherein the control circuitry includes mode register circuitry to store a mode value for each of the N bit processing units.

6. The DAC according to claim 5 , wherein the control circuitry independently enables/disables the third switch circuitry of each of the N bit processing units based on the corresponding mode value.

7. The DAC according to claim 5 , wherein each mode value comprises a flag bit, and wherein the third switch circuitry is enabled/disabled based on the flag bit.

8. A method of operation in a digital-to-analog converter (DAC), the method comprising:

receiving a digital word of N bits;

providing an array of N bit processing units disposed in parallel, the N bit processing units to receive the digital word of N bits;

wherein for each of the N bit processing units

generating a first output state with a first switch circuit, the first output state based on a first value of a received one of the N bits;

generating a second output state with a second switch circuit, the second output state based on a second value of the received one of the N bits; and

selectively generating a conditional third output state by crumbling a third switch circuit to cooperate with the first switch circuit and the second switch circuit to form a tri-state DAC configuration, the conditional third output state based on a third value of the received one of the N bits, the first switch circuit and the second switch circuit forming a duel-state DAC configuration when the third switch circuit is disabled.

9. The method according to claim 8 , wherein the first, second and third output states are represented by respective first, second and third output voltages.

10. The method according to claim 8 , wherein each of the N bit processing units includes an output impedance, and wherein for each of the N bit processing units:

generating the first output state includes switching the output impedance to a high voltage source with first switch circuitry based on a first value of the received one of the N input bits;

generating the second output state includes switching the output impedance to a low voltage source with second switch circuitry based on a second value of the received one of the N input bits; and

selectively generating the conditional third output state includes switching the output impedance to an intermediate voltage source with third switch circuitry.

11. The method according to claim 10 , further comprising:

each of the N bit processing units independently enabling/disabling their respective third switch circuitry.

12. The method according to claim 11 , further comprising:

storing a mode value for each of the N bit processing units.

13. The method according to claim 12 , wherein the independently enabling/disabling the third switch circuitry is based on the corresponding mode value.

14. A voltage-mode driver, comprising:

input circuitry to selectively receive one of N bits of a digital word;

first switch circuitry to generate a first output state based on a first value of the received one of the N bits;

second switch circuitry to generate a second output state based on a second value of the received one of the N bits; and

selectively enabled third switch circuitry to generate, when enabled, a conditional third output state and to cooperate with the first switch circuitry and the second switch circuitry to define a tri-state driver, the first switch circuitry and the second switch circuitry forming a dual-state driver when the selectively enabled third switch circuitry is disabled.

15. The voltage-mode driver of claim 14 , wherein:

for a first operating mode, solely the first switch circuitry and the second switch circuitry are enabled to form the dual-state driver.

16. The voltage-mode driver of claim 15 , wherein:

for a second operating mode, the first switch circuitry, the second switch circuitry, and the third switch circuitry are enabled to form the tri-state driver.