Reference voltage training scheme
Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.
1. A computer-implemented method for double data rate (DDR) reference voltage training, comprising:
receiving a data stream, the data stream comprising a plurality of pulses generated using a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream;
receiving a clock signal, the clock signal comprising an in-phase signal and a quadrature-phase signal, the in-phase signal being orthogonal to the quadrature-phase signal;
utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples; and
adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples using a first set of logic during an initialization phase or a second set of logic during a maintenance phase, wherein the first set of logic is different from the second set of logic and the data stream comprises a test data pattern during the initialization phase and live data during the maintenance phase.
2. The computer-implemented method of claim 1 , wherein the second set of logic is maintained in a maintenance mode table, the maintenance mode table charting a relationship of the stream of in-phase samples to the stream of quadrature-phase samples for maintenance of the reference voltage.
3. The computer-implemented method of claim 1 , wherein the first set of logic is maintained in an initialization mode table, the initialization mode table charting a relationship of the stream of in-phase samples to the stream of quadrature-phase samples during initialization of the reference voltage.
4. The computer-implemented method of claim 1 , wherein the reference voltage is adjusted based on an average of a plurality of sampled triplets, the plurality of sampled triplets comprising two consecutive in-phase samples and one quadrature-phase sample, the quadrature-phase sample taken between the two consecutive in-phase samples.
5. The computer-implemented method of claim 1 , further comprising:
adjusting the clock signal based on a corresponding relationship of the stream of in-phase samples to the stream of quadrature-phase samples using the first set of logic during the initialization phase or the second set of logic during the maintenance phase.
6. The computer-implemented method of claim 5 , further comprising:
adjusting the clock signal based on an average of a plurality of sampled triplets, the plurality of sampled triplets comprising two consecutive in-phase samples and one quadrature-phase sample, the quadrature-phase sample taken between the two consecutive in-phase samples.
7. The computer-implemented method of claim 5 , wherein the clock signal is adjusted prior to adjusting the reference voltage.
8. The computer-implemented method of claim 5 , wherein the clock signal and the reference voltage are adjusted based on the corresponding relationships of the stream of in-phase samples to the stream of quadrature-phase samples.
9. A system for double data rate (DDR) reference voltage training, comprising:
a processor; and
a memory comprising instructions stored thereon, which when executed by the processor, causes a set of acts comprising:
receiving a data stream, the data stream comprising a plurality of pulses generated using a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream;
receiving a clock signal, the clock signal comprising an in-phase signal and a quadrature-phase signal, the in-phase signal being orthogonal to the quadrature-phase signal;
utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples; and
adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples using a first set of logic during an initialization phase or a second set of logic during a maintenance phase, wherein the first set of logic is different from the second set of logic and the data stream comprises a test data pattern during the initialization phase and live data during the maintenance phase.
10. The system of claim 9 , wherein the second set of logic is maintained in a maintenance mode table, the maintenance mode table charting a relationship of the stream of in-phase samples to the stream of quadrature-phase samples for maintenance of the reference voltage.
11. The system of claim 9 , wherein the first set of logic is maintained in an initialization mode table, the initialization mode table charting a relationship of the stream of in-phase samples to the stream of quadrature-phase samples during initialization of the reference voltage.
12. The system of claim 9 , wherein the reference voltage is adjusted based on an average of a plurality of sampled triplets, the plurality of sampled triplets comprising two consecutive in-phase samples and one quadrature-phase sample, the quadrature-phase sample taken between the two consecutive in-phase samples.
13. The system of claim 9 , wherein the set of acts further comprise adjusting the clock signal based on a corresponding relationship of the stream of in-phase samples to the stream of quadrature-phase samples using the first set of logic during the initialization phase or the second set of logic during the maintenance phase.
14. The system of claim 13 , wherein the clock signal is adjusted prior to adjusting the reference voltage.
15. The system of claim 13 , wherein the set of acts further comprise adjusting the clock signal based on an average of a plurality of sampled triplets, the plurality of sampled triplets comprising two consecutive in-phase samples and one quadrature-phase sample, the quadrature-phase sample taken between the two consecutive in-phase samples.
16. The system of claim 13 , wherein the clock signal and the reference voltage are adjusted based on the corresponding relationships of the stream of in-phase samples to the stream of quadrature-phase samples.
17. A non-transitory computer readable medium having stored thereon a set of instructions which, when executed by a processor, cause a set of acts for double data rate (DDR) reference voltage training, the set of acts comprising:
receiving a data stream, the data stream comprising a plurality of pulses generated using a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream;
receiving a clock signal, the clock signal comprising an in-phase signal and a quadrature-phase signal, the in-phase signal being orthogonal to the quadrature-phase signal;
utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples; and
adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples using a first set of logic during an initialization phase or a second set of logic during a maintenance phase, wherein the first set of logic is different from the second set of logic and the data stream comprises a test data pattern during the initialization phase and live data during the maintenance phase.
18. The non-transitory computer readable medium of claim 17 , wherein the second set of logic is maintained in a maintenance mode table, the maintenance mode table charting a relationship of the stream of in-phase samples to the stream of quadrature-phase samples for maintenance of the reference voltage.
19. The non-transitory computer readable medium of claim 17 , wherein the first set of logic is maintained in an initialization mode table, the initialization mode table charting a relationship of the stream of in-phase samples to the stream of quadrature-phase samples during initialization of the reference voltage.
20. The non-transitory computer readable medium of claim 17 , wherein the set of acts further comprise adjusting the clock signal based on a corresponding relationship of the stream of in-phase samples to the stream of quadrature-phase samples using the first set of logic during the initialization phase or the second set of logic during the maintenance phase.