Massive deep trench capacitor die fill for high performance application specific integrated circuit (ASIC) applications
A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.
1. A processor assembly, comprising:
an interposer disposed on a substrate;
an integrated circuit directly disposed on the interposer;
a memory circuit directly disposed on the interposer and coupled to the integrated circuit; and
a capacitor at least partially embedded in the interposer, the capacitor including:
at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure;
a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit;
a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit; and
an oxide layer electrically isolating the capacitor from the interposer.
2. The processor assembly of claim 1 , wherein the first voltage terminal in the integrated circuit is coupled to a drain voltage in a complementary metal-oxide-semiconductor circuit of the integrated circuit.
3. The processor assembly of claim 1 , wherein the second voltage terminal in the integrated circuit is coupled to a source voltage in a complementary metal-oxide-semiconductor of the integrated circuit.
4. The processor assembly of claim 1 , wherein the first capacitor terminal and the second capacitor terminal extend to a same height over the substrate as the integrated circuit and the memory circuit.
5. The processor assembly of claim 1 , wherein the non-planar dielectric structure includes a first dielectric portion positioned in a plane perpendicular to the substrate and a second dielectric portion positioned in a plane parallel to the substrate.
6. The processor assembly of claim 1 , wherein the non-planar dielectric structure includes a corrugated structure having a first plurality of dielectric layer portions positioned in a first plane parallel to the substrate and joined at each side by respective second and third pluralities of dielectric layer portions positioned in a second plane perpendicular to the substrate.
7. The processor assembly of claim 1 , wherein the first capacitor terminal is electrically coupled to a first voltage terminal in the memory circuit, and the second terminal in the capacitor is electrically coupled to a second voltage terminal in the memory circuit.
8. The processor assembly of claim 1 , further comprising a protective cap layer over the integrated circuit, the memory circuit, and the capacitor, wherein the protective cap layer has a uniform thickness in a region covering the integrated circuit, the memory circuit, and the capacitor.
9. The processor assembly of claim 1 , wherein the capacitor substantially covers an area of the interposer that is not covered by the integrated circuit and by the memory circuit.
10. The processor assembly of claim 1 , wherein the capacitor mitigates a resonance of the processor assembly in the range of approximately 30-200 MHz.
11. A system, comprising:
a printed circuit board;
a processor assembly including:
an interposer disposed on a substrate;
an integrated circuit directly disposed on the interposer;
a memory circuit directly disposed on the interposer and coupled to the integrated circuit; and
a capacitor at least partially embedded in the interposer, the capacitor including:
at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure;
a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit;
a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit; and
an oxide layer electrically isolating the capacitor from the interposer; and
a power converter disposed on the printed circuit board, the power converter including:
a first power converter terminal electrically connected to the first capacitor terminal via a first power supply line in the printed circuit board; and
a second power converter terminal electrically connected to the second capacitor terminal via a second power supply line in the printed circuit board.
12. The processor assembly of claim 11 , wherein the first voltage terminal in the integrated circuit is coupled to a drain voltage in a complementary metal-oxide-semiconductor circuit of the integrated circuit.
13. The processor assembly of claim 11 , wherein the second voltage terminal in the integrated circuit is coupled to a source voltage in a complementary metal-oxide-semiconductor of the integrated circuit.
14. The processor assembly of claim 11 , wherein the first capacitor terminal and the second capacitor terminal extend to a same height over the substrate as the integrated circuit and the memory circuit.
15. The processor assembly of claim 11 , wherein the non-planar dielectric structure includes a first dielectric portion positioned in a plane perpendicular to the substrate and a second dielectric portion positioned in a plane parallel to the substrate.
16. The processor assembly of claim 11 , wherein the non-planar dielectric structure includes a corrugated structure having a first plurality of dielectric layer portions positioned in a first plane parallel to the substrate and joined at each side by respective second and third pluralities of dielectric layer portions positioned in a second plane perpendicular to the substrate.
17. The processor assembly of claim 11 , wherein the first capacitor terminal is electrically coupled to a first voltage terminal in the memory circuit, and the second terminal in the capacitor is electrically coupled to a second voltage terminal in the memory circuit.
18. The processor assembly of claim 11 , further comprising a protective cap layer over the integrated circuit, the memory circuit, and the capacitor, wherein the protective cap layer has a uniform thickness in a region covering the integrated circuit, the memory circuit, and the capacitor.
19. The processor assembly of claim 11 , wherein the capacitor substantially covers an area of the interposer that is not covered by the integrated circuit and by the memory circuit.
20. The processor assembly of claim 11 , wherein the capacitor mitigates a resonance of the processor assembly in the range of approximately 30-200 MHz.