Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices

1. A method for manufacturing a semiconductor device, comprising:

forming a first vertical transistor on a semiconductor substrate;

forming a second vertical transistor stacked on the first vertical transistor; and

forming a silicide layer on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor, wherein the silicide layer electrically connects the first and second drain regions to each other;

wherein forming the silicide layer comprises:

forming a sacrificial layer on the first and second drain regions;

removing the sacrificial layer to expose the first and second drain regions; and

performing a silicidation process to form the silicide layer.

2. The method according to claim 1 , wherein the first vertical transistor comprises a floating gate.

3. The method according to claim 1 , wherein forming the first vertical transistor comprises:

forming a bottom source region on a semiconductor substrate;

forming a first channel region extending vertically from the bottom source region;

forming the first drain region on an upper portion of the first channel region; and

forming a first gate region around the first channel region.

4. The method according to claim 3 , wherein forming the second vertical transistor comprises:

forming the second drain region on an upper portion of the first drain region;

forming a second channel region extending vertically from the second drain region;

forming a top source region on an upper portion of the second channel region; and

forming a second gate region around the second channel region.

5. The method according to claim 4 , wherein the first gate region comprises a first gate metal layer formed on a first high-K dielectric layer, and the second gate region comprises a second gate metal layer formed on a second high-K dielectric layer.

6. The method according to claim 4 , further comprising forming an additional silicide layer on the top source region.

7. The method according to claim 1 , wherein the first vertical transistor is a p-type field effect transistor (PFET) and the second vertical transistor is an n-type field effect transistor (NFET).

8. The method according to claim 1 , wherein the first and second drain regions have different doping types from each other.

9. The method according to claim 1 , further comprising forming a contact layer to the first and second drain regions.

10. A method for manufacturing a semiconductor device, comprising:

forming a first vertical transistor on a semiconductor substrate;

forming a second vertical transistor stacked on the first vertical transistor; and

forming a silicide layer on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor, wherein the silicide layer electrically connects the first and second drain regions to each other;

wherein forming the first vertical transistor comprises:

forming a bottom source region on a semiconductor substrate;

forming a first channel region extending vertically from the bottom source region;

forming the first drain region on an upper portion of the first channel region; and

forming a first gate region around the first channel region;

wherein forming the second vertical transistor comprises:

forming the second drain region on an upper portion of the first drain region;

forming a second channel region extending vertically from the second drain region;

forming a top source region on an upper portion of the second channel region; and

forming a second gate region around the second channel region;

wherein the first gate region comprises a first gate metal layer formed on a first high-K dielectric layer, and the second gate region comprises a second gate metal layer formed on a second high-K dielectric layer; and

wherein the first high-K dielectric layer has a greater thickness than the second high-K dielectric layer.

11. A method for manufacturing a semiconductor device, comprising:

forming a first vertical transistor on a semiconductor substrate;

forming a second vertical transistor stacked on the first vertical transistor;

forming a silicide layer on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor, wherein the silicide layer electrically connects the first and second drain regions to each other;

wherein forming the first vertical transistor comprises:

forming a bottom source region on a semiconductor substrate;

forming a first channel region extending vertically from the bottom source region;

forming the first drain region on an upper portion of the first channel region; and

forming a first gate region around the first channel region;

wherein forming the second vertical transistor comprises:

forming the second drain region on an upper portion of the first drain region;

forming a second channel region extending vertically from the second drain region;

forming a top source region on an upper portion of the second channel region; and

forming a second gate region around the second channel region;

forming a first dummy gate layer around the first channel region and forming a first dummy gate layer around the first channel region prior to forming the first and second gate regions; and

replacing the first and second dummy gate layers with the first and second gate regions respectively;

wherein the first and second dummy gate layers comprise different materials from each other.

12. The method according claim 11 , wherein replacing the first and second dummy gate layers with the first and second gate regions comprises:

selectively removing the first dummy gate layer with respect to the second dummy gate layer; and

depositing a high-K dielectric material on the first channel region in an area left vacant by the removal of the first dummy gate layer to form a first high-K dielectric layer.

13. The method according to claim 12 , wherein replacing the first and second dummy gate layers with the first and second gate regions further comprises:

removing the second dummy gate layer; and

depositing additional high-K dielectric material on the second channel region in an area left vacant by the removal of the second dummy gate layer to form a second high-K dielectric layer; and

depositing the additional high-K material on the first high-K dielectric layer, wherein a thickness of the first high-K dielectric layer is increased by the deposition of the additional high-K material on the first high-K dielectric layer.