Imaging systems with sub-radix-2 charge sharing successive approximation register (SAR) analog-to-digital converters
View Patent ↗An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.
1. A data converter, comprising:
a comparator configured to receive an input signal;
a charge sharing digital-to-analog converter configured to output signals that are received by the comparator; and
control logic configured to receive signals from the comparator and output signals to the charge sharing digital-to-analog converter, wherein the charge sharing digital-to-analog converter comprises capacitors sized using a sub-radix-2 scaling scheme.
2. The data converter of claim 1 , wherein the comparator exhibits a comparator offset and wherein the sub-radix-2 scaling scheme provides a redundancy margin for improving tolerance to the comparator offset.
3. The data converter of claim 1 , wherein the control logic is successive approximation register control logic.
4. The data converter of claim 3 , wherein the data converter has a resolution that exceeds 8 bits.
5. The data converter of claim 3 , wherein the data converter has at least 10 bits of resolution.
6. The data converter of claim 3 , wherein the capacitors in the charge sharing digital-to-analog converter are all pre-charged to a known reference voltage level.
7. The data converter of claim 1 , wherein the sub-radix-2 scaling scheme has a scaling factor ranging from 1.5 to 1.9999.
8. The data converter of claim 1 , wherein the capacitors in the charge sharing digital-to-analog converter comprise a first set of capacitors sized using a first sub-radix-2 scaling factor and a second set of capacitors sized using a second scaling factor that is different than the first sub-radix-2 scaling factor.
9. A data converter, comprising:
a comparator having an input;
a digital-to-analog converter having a plurality of capacitors that are selectively coupled in parallel to the input of the comparator, wherein each capacitor has a respective capacitance that differs from a capacitance of at least one other capacitor by a scaling factor that is between 1.5 and 1.9999; and
control logic configured to receive signals from the comparator and output signals to the digital-to-analog converter.
10. The data converter of claim 9 , wherein the digital-to-analog converter is a charge sharing digital-to-analog converter.
11. The data converter of claim 10 , wherein the control logic is successive approximation register control logic.
12. The data converter of claim 11 , wherein the data converter has a resolution that exceeds 8 bits.
13. The data converter of claim 11 , wherein the data converter has at least 10 bits of resolution.
14. The data converter of claim 11 , wherein the capacitors in the charge sharing digital-to-analog converter are all pre-charged to a known reference voltage level.
15. A data converter, comprising:
a comparator configured to receive an input signal;
a charge sharing digital-to-analog converter configured to generate an analog signal, wherein the comparator is further configured to compare the input signal to the analog signal; and
successive-approximation-register control logic configured to receive signals from the comparator and output signals to the charge sharing digital-to-analog converter, wherein the data converter has at least 9 bits of resolution.
16. The data converter of claim 15 , wherein the charge sharing digital-to-analog converter includes capacitors that are all pre-charged to a known reference voltage level.
17. The data converter of claim 16 , wherein the capacitors have weights that are digitally calibrated.
18. The data converter of claim 16 , wherein at least some of the capacitors are scaled using a first factor that is less than 2.
19. The data converter of claim 16 , wherein a first subset of the capacitors are scaled using a first factor that is less than 2 and wherein a second subset of the capacitors are scaled using a second factor that is between 1.5 to 2.