IP Library › Granted Patent US 10,811,060
Granted Patent B2
US 10,811,060 · App. 16/361,792 · Granted Oct 20, 2020

Information processing apparatus and control method thereof

Inventor: Daisuke Matsunaga (Tokyo, JP)
Assignee: Canon Kabushiki Kaisha
G11C5/148G11C5/147G11C11/417
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Quick Facts
Patent No.
US 10,811,060
App. No.
16/361,792
Granted
Oct 20, 2020
Kind
B2
Abstract

The information processing includes: a first SRAM configured to store a parameter for performing data processing for data input to a data processing unit configured to perform the data processing; a second SRAM configured to temporarily store data processed by the data processing unit; a data control unit configured to control an output of the data stored in the second SRAM; and a control unit configured to perform power control to supply power to a storage area in which the parameter of the first SRAM is stored, stop power supply to a control area for writing the data to the first SRAM and a storage area in which the data of the second SRAM is stored, and stop power supply to a control area for writing the data in a case where a job that uses the first SRAM and the second SRAM is not performed.

Claims (46)

1. An information processing apparatus comprising:

a data processing unit configured to perform data processing;

a first SRAM configured to store a parameter for performing the data processing for data input to the data processing unit;

a second SRAM configured to temporarily store data processed by the data processing unit;

a data control unit configured to control an output of the data stored in the second SRAM;

a control unit configured to perform power control to supply power to a storage area of the first SRAM in which the parameter is stored, stop power supply to a control area for writing the data to the first SRAM and a storage area of the second SRAM in which the data is stored, and stop power supply to a control area for writing the data in a case where a job that uses the first SRAM and the second SRAM is not performed; and

an output unit configured to output a control signal for causing the first SRAM and the second SRAM to make a transition into a power saving mode to the first SRAM and the second SRAM connected serially.

2. The information processing apparatus according to claim 1 , wherein

the control unit supplies power to the storage area and the control area, both the areas of the first SRAM, and supplies power to the storage area and the control area, both the areas of the second SRAM, in a case where a job that uses the first SRAM and the second SRAM is performed.

3. The information processing apparatus according to claim 1 , wherein

data input to the data processing unit is image data and

the parameter is a lookup table referred to by the data processing unit.

4. The information processing apparatus according to claim 3 , wherein

the lookup table is a conversion table referred to in color space conversion processing of the image data.

5. The information processing apparatus according to claim 1 , wherein

the second SRAM delays an output of data processed by the data processing unit.

6. An information processing apparatus comprising a plurality of volatile memory devices, wherein each of the volatile memory devices has a memory area, a control area configured to control a write to the memory area, and a power control circuit configured to control power supply to the memory area and the control area, and wherein

the information processing apparatus comprises a power controller configured to provide a signal for causing a transition into a power saving state,

the power control circuit of at least one volatile memory device of the plurality of volatile memory devices stops power supply to the control area while continuing power supply to the memory area based on the signal from the power controller, and

the power control circuit of another volatile memory device of the plurality of volatile memory devices stops power supply to the memory area and the control area based on the signal from the power controller.

7. The information processing apparatus according to claim 6 , wherein

after causing a transition into the power saving state, power is supplied to the power control circuit of the volatile memory device.

8. The information processing apparatus according to claim 6 , further comprising:

a data processing unit configured to process input data, wherein

the at least one volatile memory device stores a parameter used in processing by the data processing unit.

9. The information processing apparatus according to claim 8 , wherein

the parameter stored in the at least one volatile memory device is a lookup table.

10. The information processing apparatus according to claim 6 , wherein

one of the at least one volatile memory device of the plurality of volatile memory devices delays the signal from the power controller and then outputs the signal to the another volatile memory device.

11. The information processing apparatus according to claim 6 , wherein

the power control circuit determines an area to which power supply is stopped of the memory area and the control area based on a voltage applied to a predetermined pin.

12. The information processing apparatus according to claim 6 , wherein

the power controller gives the signal to cause a transition into the power saving state in accordance with completion of a job to access the volatile memory device.

13. The information processing apparatus according to claim 6 , wherein

the volatile memory device is an SRAM.

14. The information processing apparatus according to claim 12 , wherein

the power controller instructs the volatile memory device to return from the power saving state in accordance with a job being input.

15. The information processing apparatus according to claim 6 , wherein

for each of the volatile memory devices, a setting is made as to whether to stop power supply to the control area while continuing power supply to the memory area based on the signal from the power controller, or to stop power supply to the memory area and the control area.

16. The information processing apparatus according to claim 6 , wherein the one of the at least one volatile memory device of the plurality of volatile memory devices receives the signal from the power controller and outputs the signal to the another volatile memory device.

17. A control method of an information processing apparatus, the control method comprising:

a data processing step of performing data processing;

a step of storing a parameter for performing the data processing for data input at the data processing step in a first storage unit;

a step of temporarily storing data processed at the data processing step in a second storage unit;

a data control step of controlling an output of the data stored in the second storage unit; and

a control step of performing power control to supply power to a storage area in which the parameter of the first storage unit is stored, stop power supply to a control area for writing the data to the first storage unit a storage area in which the data of the second storage area is stored, and stop power supply to a control area for writing the data in a case where a job that uses the first storage unit and the second storage unit is not performed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2019
From: MATSUNAGA, DAISUKE
To: CANON KABUSHIKI KAISHA
Reel/Frame 049388/0632 →
Priority Claims (2)
JP 2018-060895 · Mar 27, 2018 · national
JP 2018-243004 · Dec 26, 2018 · national
Continuity (1)
Related Publication 20190304514A1 · Oct 3, 2019