Three-dimensional memory device including composite word lines and multi-strip select lines and method for making the same
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
1. A three-dimensional memory device comprising:
a first alternating stack of insulating layers and electrically conductive layers located over a substrate; and
memory stack structures extending through the first alternating stack;
wherein:
the electrically conductive layers comprise drain-select-level electrically conductive layers located in at least two different levels having different vertical distances from the substrate and laterally spaced apart as multiple groups that are electrically isolated from one another;
the electrically conductive layers further comprise word-line-level electrically conductive layers that underlie the drain-select-level electrically conductive layers and comprise a respective pair of sidewalls that laterally extend along a first horizontal direction;
each of the word-line-level electrically conductive layers comprises a respective first electrically conductive material layer including a first electrically conductive material and a respective second electrically conductive material layer comprising a second electrically conductive material that is different from the first electrically conductive material and formed within the respective first electrically conductive material layer;
each of the drain-select-level electrically conductive layers consists essentially of the first electrically conductive material; and
wherein the three dimensional memory device includes a feature selected from the following features:
a first feature wherein the drain-select-level electrically conductive layers do not contact any of the second electrically conductive material; or
a second features wherein each laterally neighboring pair of groups selected from the multiple groups is laterally spaced apart by a respective encapsulated cavity that is free of any solid material therein; or
a third feature wherein drain-select-level electrically conductive layers within each group selected from the multiple groups are electrically isolated from each other or one another and each of the drain-select-level electrically conductive layers within each group comprise a sidewall that contacts an element selected from:
a cavity that is free of any solid material; and
a vertically extending portion of an insulating material that overlies and surrounds a cavity; or
a fourth feature wherein drain-select-level electrically conductive layers within each group selected from the multiple groups are electrically connected by at least one vertical conductive strip comprising the first electrically conductive material, wherein each of the at least one vertical conductive strip is not in direct contact with any surface of the second electrically conductive material; or
a fifth feature wherein each of the drain-select-level electrically conductive layers has a respective vertical thickness that is less than twice a vertical thickness of horizontal portions of the first electrically conductive material layers within the word-line-level electrically conductive layers.
2. The three-dimensional memory device of claim 1 , wherein the feature is the first feature.
3. The three-dimensional memory device of claim 1 , wherein the feature is the second feature.
4. The three-dimensional memory device of claim 3 , wherein:
the word-line-level electrically conductive layers have a uniform word-line-level width along a second horizontal direction that is perpendicular to the first horizontal direction; and
each of the drain-select-level electrically conductive layers laterally extends along the first horizontal direction and has a respective uniform drain-select-level width along the second horizontal direction that is less than one third of the uniform word-line-level width.
5. The three-dimensional memory device of claim 1 , wherein:
the first electrically conductive material consists essentially of a first elemental metal; and
the second electrically conductive material consists essentially of a second elemental metal.
6. The three-dimensional memory device of claim 5 , wherein:
the first elemental metal comprises tungsten; and
the second elemental metal comprises a metal selected from molybdenum, cobalt, or ruthenium.
7. The three-dimensional memory device of claim 1 , wherein each horizontal surface of the second electrically conductive material layers contacts a horizontal surface of the first electrically conductive material layers.
8. The three-dimensional memory device of claim 7 , further comprising conformal insulating spacers contacting sidewalls of the insulating layers and sidewalls of the electrically conductive layers, wherein each sidewall of the second electrically conductive material layers contacts a sidewall of the first electrically conductive material layers or a sidewall of the conformal insulating spacers.
9. The three-dimensional memory device of claim 1 , wherein the feature is the third feature.
10. The three-dimensional memory device of claim 1 , wherein the feature is the fourth feature.
11. The three-dimensional memory device of claim 10 , wherein each sidewall of the at least one vertical conductive strip contacts an element selected from:
one of the insulating layers;
a cavity that is free of any solid material; and
a vertically extending portion of an insulating material that overlies and surrounds a cavity.
12. The three-dimensional memory device of claim 10 , wherein each of the at least one vertical conductive strip has a lateral thickness that is the same as a vertical thickness of horizontal portions of the first electrically conductive material layers.
13. The three-dimensional memory device of claim 1 , wherein the feature is the fifth feature.
14. The three-dimensional memory device of claim 1 , each of the electrically conductive layers includes a sidewall that is laterally offset from a sidewall of a most proximal one of the insulating layers by a same lateral offset distance.
15. A method of forming a semiconductor structure comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate, wherein the sacrificial material layers comprise word-line-level sacrificial material layers and drain-select-level sacrificial material layers that overlie the word-line-level sacrificial material layers and have a lesser thickness than the word-line-level sacrificial material layers;
forming memory stack structures through the alternating stack;
forming drain-select-level trenches through an upper subset of the sacrificial material layers;
forming backside trenches through each layer of the alternating stack;
forming word-line-level backside recesses and drain-select-level backside recesses by removing the word-line-level sacrificial material layers and the drain-select-level sacrificial material layers, respectively;
depositing a first continuous electrically conductive material layer including a first electrically conductive material to fill all volumes of the drain-select-level backside recesses and to partially fill volumes of the drain-select-level backside recesses;
depositing a second continuous electrically conductive material layer including a second electrically conductive material in unfilled volumes of the word-line-level backside recesses; and
removing at least partially portions of the second electrically conductive material and the first electrically conductive material from the drain-select-level trenches, wherein drain-select-level electrically conductive layers are provided in volumes of the drain-select-level backside recesses as multiple groups that are laterally spaced apart and electrically isolated from one another.
16. The method of claim 15 , further comprising:
isotropically removing the first electrically conductive material and the second electrically conductive material from the backside trenches and from above a topmost one of the insulating layers by an isotropic recess etch process, wherein electrically conductive layers including remaining portions of the first and second continuous electrically conductive layers are formed in the backside recesses and in the drain-select-level trenches;
anisotropically etching the second electrically conductive material in drain-select-level cavities selective to the first electrically conductive material; and
etching physically exposed portions of the first electrically conductive material from the drain-select-level cavities, wherein remaining portions of the electrically conductive layers include multiple groups of drain-select-level electrically conductive layers that are laterally spaced apart and electrically isolated from one another.
17. The method of claim 16 , wherein:
etching the physically exposed portions of the first electrically conductive material from the drain-select-level cavities comprises performing an anisotropic etch process that partially etches portions of the first electrically conductive material in the drain-select-level trenches; and
each drain-select-level electrically conductive layer within each group selected from the multiple groups are electrically connected to and from each other or one another by at least one vertical conductive strip comprising the first electrically conductive material within a respective one of the drain-select-level trenches.
18. The method of claim 16 , wherein:
etching the physically exposed portions of the first electrically conductive material from the drain-select-level cavities comprises completely removing the first electrically conductive material from the drain-select-level trenches; and
each drain-select-level electrically conductive layer within each group selected from the multiple groups are electrically isolated from each other or one another.
19. The method of claim 15 , further comprising anisotropically depositing a nonconformal insulating layer over the sidewalls of the insulating layers that are exposed to the backside trenches and over the drain-select-level trenches, wherein an encapsulated cavity that is free of any solid material therein and bounded by a bottom surface of the nonconformal insulating layer is formed in a volume of one of the drain-select-level trenches.