Semiconductor memory device having a semiconductor chip including a memory cell and a resistance element

1. A method for controlling a memory system including a controller chip and at least one non-volatile memory chip which includes a calibration control circuit, a first output buffer circuit, and a first resistance element, the method comprising:

receiving a read command from the controller chip;

setting a ready/busy signal to a busy state based on the read command;

executing a calibration operation which controls an impedance of the first output buffer circuit based on the read command;

setting the ready/busy signal to a ready state; and

sending data to the controller chip in response to the read command,

wherein the calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.

2. The method for controlling the memory system according to claim 1 , further comprising:

sensing a temperature of the at least one non-volatile memory chip by a temperature sensor of the at least one non-volatile memory chip; and

controlling a resistance value of the first resistance element based on a sense result of the temperature.

3. The method for controlling the memory system according to claim 1 , wherein the calibration operation is executed in synchronization with the receiving the read command.

4. The method for controlling the memory system according to claim 1 , wherein the at least one non-volatile memory chip is a chip of a NAND flash memory.

5. The method for controlling the memory system according to claim 1 , wherein:

the at least one non-volatile memory chip further includes a first terminal, and

the first resistance element is connected to the first terminal.

6. The method for controlling the memory system according to claim 1 , wherein:

the at least one non-volatile memory chip further includes a second terminal and a first interconnect electrically separated from the second terminal,

a first voltage is supplied to the second terminal, and

a second voltage is supplied to the first output buffer circuit through the first interconnect.

7. The method for controlling the memory system according to claim 6 , wherein:

the at least one non-volatile memory chip further includes a third terminal connected to the first interconnect, and

the second voltage is supplied to the third terminal.

8. The method for controlling the memory system according to claim 6 , wherein:

the at least one non-volatile memory chip further includes a fourth terminal and a fifth terminal electrically separated from the fourth terminal,

a third voltage lower than the first voltage is supplied to the fourth terminal, and

a fourth voltage lower than the second voltage is supplied to the fifth terminal.

9. The method for controlling the memory system according to claim 1 , wherein:

the at least one non-volatile memory chip comprises a plurality of non-volatile memory chips,

each of the plurality of non-volatile memory chips includes the first resistance element, and

each of the plurality of non-volatile memory chips executes the calibration operation using the first resistance element.

10. The method for controlling the memory system according to claim 9 , wherein, when the controller chip commands the plurality of non-volatile memory chips to perform an operation, a signal level of a chip enable signal of a memory chip to be an operation target among the plurality of non-volatile memory chips is set at a level indicating the operation target.

11. The method for controlling the memory system according to claim 1 , wherein the first resistance element is directly connected to the calibration control circuit.