Transistor device with (anti)ferroelectric spacer structures
Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.
1. An integrated circuit (IC) device comprising:
a fin structure comprising doped source or drain regions, and a channel region between the doped source or drain regions;
a layer on the channel region, the layer comprising a dielectric material;
spacers which each extend over a different respective one of the doped source or drain regions, the spacers comprising a first spacer which comprises:
a first portion comprising a ferroelectric or anti-ferroelectric material; and
a second portion comprising a material other than the ferroelectric or anti-ferroelectric material, wherein the first portion is offset vertically from the second portion; and
a gate electrode which extends over the layer in a region between the spacers.
2. The IC device of claim 1 , wherein the first spacer comprises multiple ferroelectric or anti-ferroelectric portions which are interleaved with one or more other portions.
3. The IC device of claim 1 , wherein the first portion extends vertically alongside the second portion.
4. The IC device of claim 3 , wherein the first spacer comprises multiple ferroelectric or anti-ferroelectric portions which are interleaved with one or more other portions.
5. The IC device of claim 1 , wherein the first portion forms a bottom of the first spacer.
6. The IC device of claim 1 , wherein a total vertical span of the first portion is in a range of 5% to 80% of a total vertical span of the first spacer.
7. The IC device of claim 6 , wherein the total vertical span of the first portion is in a range of 10% to 50% of the total vertical span of the first spacer.
8. The IC device of claim 1 , wherein the ferroelectric or anti-ferroelectric material comprises hafnium, oxygen, and one of zirconium, aluminum, silicon, yttrium, scandium, lanthanum, nitrogen, or molybdenum.
9. The IC device of claim 1 , wherein the ferroelectric or anti-ferroelectric material comprises:
oxygen;
one of lutetium, bismuth, lead, barium, lanthanum, or strontium; and
one of iron, titanium, cobalt, tantalum, niobium, ruthenium, or zinc.
10. The IC device of claim 9 , wherein the ferroelectric or anti-ferroelectric material comprises a compound ABO3, where A is one of lutetium, bismuth, lead, barium, lanthanum, or strontium, and where B is one of iron, titanium, cobalt, tantalum, niobium, ruthenium, or zinc.
11. An integrated circuit (IC) device comprising:
doped source or drain regions of a transistor;
a channel region of the transistor, the channel region disposed between the doped source or drain regions; and
spacers which each extend over a different respective one of the doped source or drain regions, the spacers comprising a first spacer which comprises:
a first portion comprising a ferroelectric or anti-ferroelectric material; and
a second portion comprising a material other than the ferroelectric or anti-ferroelectric material, wherein the first portion is offset vertically from the second portion.
12. The IC device of claim 11 , wherein the first portion forms a bottom of the first spacer.
13. The IC device of claim 11 , wherein a total vertical span of the first portion is in a range of 5% to 80% of a total vertical span of the first spacer.
14. The IC device of claim 11 , wherein the ferroelectric or anti-ferroelectric material comprises hafnium, oxygen, and one of zirconium, aluminum, silicon, yttrium, scandium, lanthanum, nitrogen, or molybdenum.
15. The IC device of claim 11 , wherein the ferroelectric or anti-ferroelectric material comprises:
oxygen;
one of lutetium, bismuth, lead, barium, lanthanum, or strontium; and
one of iron, titanium, cobalt, tantalum, niobium, ruthenium, or zinc.
16. A system comprising:
an integrated circuit (IC) device comprising:
a transistor structure comprising:
a fin structure comprising doped source or drain regions, and a channel region between the doped source or drain regions;
a layer on the channel region, the layer comprising a dielectric material;
spacers which each extend over a different respective one of the doped source or drain regions, the spacers comprising a first spacer which comprises:
a first portion comprising a ferroelectric or anti-ferroelectric material; and
a second portion comprising a material other than the ferroelectric or anti-ferroelectric material, wherein the first portion is offset vertically from the second portion; and
a gate electrode which extends over the layer in a region between the spacers; and
a display device coupled to the IC device, the display device to display an image based on a signal communicated with the transistor structure.
17. The system of claim 16 , wherein the ferroelectric or anti-ferroelectric material comprises hafnium, oxygen, and one of zirconium, aluminum, silicon, yttrium, scandium, lanthanum, nitrogen, or molybdenum.