Electrical isolation for nanosheet transistor devices

1. A method of fabricating a nanosheet transistor structure, comprising:

obtaining a monolithic structure including a semiconductor substrate and a vertical stack of nanosheet channel layers comprising silicon and sacrificial semiconductor layers comprising silicon germanium on the semiconductor substrate, the nanosheet channel layers and the sacrificial semiconductor layers being arranged in alternating sequence;

forming first and second vertical trenches through the vertical stack down to the semiconductor substrate;

conducting a directional first etch, thereby forming first and second recesses within the semiconductor substrate, the first recess extending vertically from the first vertical trench and the second recess extending vertically from the second vertical trench;

conducting a self-limiting second etch following the directional first etch, thereby forming first and second cavities within the semiconductor substrate extending, respectively, from the first and second vertical trenches and beneath, respectively, the first and second recesses, the first and second cavities merging beneath a portion of the vertical stack;

filling the first and second recesses and the first and second cavities with an electrically insulating material;

removing end portions of the sacrificial semiconductor layers adjoining the first and second vertical trenches, thereby forming indented regions between the nanosheet channel layers;

forming dielectric inner spacers within the indented regions;

epitaxially growing first and second source/drain regions on the nanosheet channel layers, the first source/drain region being grown within the first vertical trench and directly over the first cavity, the second source/drain region being grown within the second vertical trench and directly over the second cavity;

replacing the sacrificial semiconductor layers with a gate dielectric layer and gate metal.

2. The method of claim 1 , wherein the self-limiting second etch terminates at <111> crystal planes of the semiconductor substrate.

3. The method of claim 1 , further including first and second shallow trench isolation regions extending within the semiconductor substrate, and further wherein the first cavity contacts the first shallow trench isolation region and the second cavity contacts the second shallow trench isolation region.

4. The method of claim 1 , further including:

forming a sacrificial gate layer over the vertical stack and the semiconductor substrate;

patterning the sacrificial gate layer, thereby forming first and second trench openings within the sacrificial gate layer and over the vertical stack; and

wherein the first and second vertical trenches through the vertical stack are respectively formed in vertical alignment with the first and second trench openings within the sacrificial gate layer.

5. The method of claim 4 , further including forming a sidewall spacer layer on the sacrificial gate layer and extending within the first and second trench openings.

6. The method of claim 1 , further including:

forming a sidewall liner within the first and second vertical trenches prior to forming the first and second cavities; and

removing the sidewall liner prior to epitaxially growing the first and second source/drain regions.

7. The method of claim 1 , wherein filling the first and second recesses and the first and second cavities with an electrically insulating material includes introducing a high density plasma chemical vapor deposited oxide within the first and second recesses and the first and second cavities.

8. A method of fabricating a nanosheet transistor structure comprising:

obtaining a monolithic structure including a semiconductor substrate comprising silicon, a vertical stack of nanosheet channel layers and sacrificial semiconductor layers on the semiconductor substrate, the nanosheet channel layers and the sacrificial semiconductor layers being arranged in alternating sequence, and a sacrificial gate layer extending over the vertical stack;

forming first and second trenches within the sacrificial gate layer, the first and second trenches extending vertically downwardly towards the vertical stack;

extending the first and second trenches through the vertical stack down to the semiconductor substrate;

conducting a directional first etch to form first and second recesses within the semiconductor substrate, the first recess extending vertically from the first trench and the second recess extending vertically from the second trench;

conducting a self-limiting second etch following the directional first etch to form first and second cavities beneath, respectively, the first and second recesses, the first and second cavities merging beneath a portion of the vertical stack;

filling the first and second recesses and the first and second cavities with an electrically insulating material;

removing end portions of the sacrificial semiconductor layers adjoining the first and second trenches to form indented regions between the nanosheet channel layers;

forming dielectric inner spacers within the indented regions; and

epitaxially growing first and second source/drain regions on the nanosheet channel layers, the first source/drain region being grown within the first trench and directly over the first cavity, the second source/drain region being grown within the second trench and directly over the second cavity.

9. The method of claim 8 , wherein the nanosheet channel layers comprise silicon and the sacrificial semiconductor layers comprise silicon germanium.

10. The method of claim 9 , further including:

replacing the sacrificial semiconductor layers with a gate dielectric layer and gate metal.

11. The method of claim 8 , further including first and second shallow trench isolation regions extending within the semiconductor substrate, and further wherein the first cavity contacts the first shallow trench isolation region and the second cavity contacts the second shallow trench isolation region.

12. The method of claim 11 , wherein the sacrificial semiconductor layers comprise silicon germanium.

13. The method of claim 8 , wherein filling the first and second recesses and the first and second cavities with an electrically insulating material includes introducing a high density plasma chemical vapor deposited oxide within the first and second recesses and the first and second cavities.

14. The method of claim 8 , wherein the self-limiting second etch terminates at <111> crystal planes of the semiconductor substrate.