Hardware acceleration using a self-programmable coprocessor architecture

1. A method for hardware acceleration using a self-programmable coprocessor architecture, the method comprising:

determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence;

responsive to determining that the instruction cache comprises an accelerable instruction sequence:

instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and

receiving, from the accelerator complex, a result of the complex instruction;

responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence:

determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image; and

synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence.

2. The method of claim 1 , wherein determining that the instruction cache comprises an accelerable instruction sequence comprises determining that a value stored in a Multiple Input Signature Register (MISR) corresponds to the complex instruction, wherein the MISR is configured to receive, as input, a plurality of instructions from the instruction cache.

3. The method of claim 1 , further comprising:

determining that the instruction cache comprises the potentially accelerable instruction sequence;

determining that the other complex instruction for the potentially accelerable instruction sequence corresponds to an accelerator image not deployed to the accelerator complex; and

configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction.

4. The method of claim 3 , wherein configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction comprises providing, to the accelerator complex, the accelerator image not deployed to the accelerator complex.

5. The method of claim 4 , further comprising determining to configure, based on the accelerator image not deployed to the accelerator complex, the accelerator block based on one or more of: a number of available accelerator blocks, a frequency of accelerator block access, a verification of the accelerator image not deployed to the accelerator complex, or an estimated speedup.

6. The method of claim 1 , further comprising verifying the synthesized accelerator image including comparing results of executing the potentially accelerable instruction sequence by the processor core with an output of the synthesized accelerator image.

7. The method of claim 6 , further comprising storing the synthesized accelerator image in a Complex Instruction Library comprising one or more entries each associating one of a plurality of complex instructions with a corresponding accelerator image.

8. An apparatus for hardware acceleration using a self-programmable coprocessor architecture configured to carry out the steps of:

determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence;

responsive to determining that the instruction cache comprises an accelerable instruction sequence:

instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and

receiving, from the accelerator complex, a result of the complex instruction;

responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence:

determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image; and

synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence.

9. The apparatus of claim 8 , wherein determining that the instruction cache comprises an accelerable instruction sequence comprises determining that a signature generated by a Multiple Input Signature Register (MISR) corresponds to the complex instruction, wherein the MISR is configured to receive, as input, a plurality of instructions from the instruction cache.

10. The apparatus of claim 8 , wherein the steps further comprise:

determining that the instruction cache comprises the potentially accelerable instruction sequence;

determining that the other complex instruction for the potentially accelerable instruction sequence corresponds to an accelerator image not deployed to the accelerator complex; and

configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction.

11. The apparatus of claim 10 , wherein configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction comprises providing, to the accelerator complex, the accelerator image not deployed to the accelerator complex.

12. The apparatus of claim 11 , wherein the steps further comprise determining to configure, based on the accelerator image not deployed to the accelerator complex, the accelerator block based on one or more of: a number of available accelerator blocks, a frequency of accelerator block access, a verification of the accelerator image not deployed to the accelerator complex, or an estimated speedup.

13. The apparatus of claim 8 , further comprising verifying the synthesized accelerator image including comparing results of executing the potentially accelerable instruction sequence by the processor core with an output of the synthesized accelerator image.

14. The apparatus of claim 13 , wherein the steps further comprise storing the synthesized accelerator image in a Complex Instruction Library comprising one or more entries each associating one of a plurality of complex instructions with a corresponding accelerator image.

15. A computer program product for hardware acceleration using a self-programmable coprocessor architecture, the computer program product disposed upon a non-transitory computer readable storage medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

determining that an instruction cache comprises either an accelerable instruction sequence or a potentially accelerable instruction sequence;

responsive to determining that the instruction cache comprises an accelerable instruction sequence:

instead of executing, by a processor core, the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising a plurality of accelerator blocks, a complex instruction corresponding to the accelerable instruction sequence, wherein the accelerator block comprises one or more reprogrammable logic elements configured to execute the complex instruction; and

receiving, from the accelerator complex, a result of the complex instruction;

responsive to determining that the instruction cache comprises the potentially accelerable instruction sequence:

determining that another complex instruction for the potentially accelerable instruction sequence does not correspond to any accelerator image;

synthesizing, based on the potentially accelerable instruction sequence, a accelerator image in parallel to executing, by the processor core, the potentially accelerable instruction sequence; and

verifying the synthesized accelerator image.

16. The computer program product of claim 15 , wherein determining that the instruction cache comprises an accelerable instruction sequence comprises determining that a value stored in a Multiple Input Signature Register (MISR) corresponds to the complex instruction, wherein the MISR is configured to receive, as input, a plurality of instructions from the instruction cache.

17. The computer program product of claim 16 , wherein the steps further comprise:

determining that the instruction cache comprises the potentially accelerable instruction sequence;

determining that the other complex instruction for the potentially accelerable instruction sequence corresponds to an accelerator image not deployed to the accelerator complex; and

configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction.

18. The computer program product of claim 17 , wherein configuring, based on the accelerator image not deployed to the accelerator complex, the accelerator block of the reprogrammable accelerator to execute the other complex instruction comprises providing, to the accelerator complex, the accelerator image not deployed to the accelerator complex.

19. The computer program product of claim 18 , wherein the steps further comprise determining to configure, based on the accelerator image not deployed to the accelerator complex, the accelerator block based on one or more of: a number of available accelerator blocks, a frequency of accelerator block access, a verification of the accelerator image not deployed to the accelerator complex, or an estimated speedup.

20. The computer program product of claim 15 , wherein verifying the synthesized accelerator image includes comparing results of executing the potentially accelerable instruction sequence by the processor core with an output of the synthesized accelerator image.