PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SOC) AGENT RESET AND POWER MANAGEMENT
A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
1 . A System on a Chip (SoC), comprising:
an interconnect;
an IP agent provided on the SoC and arranged to communicate with the interconnect; and
a reset manager for initiating a reset of the IP agent, the reset involving a negotiation between the interconnect and the IP agent that results in the IP agent becoming transaction ready.
2 . The SoC of claim 1 , wherein the negotiation involves the interconnect generating at least one inquiry for the IP agent, the at least one inquiry requesting an “awake” status of the IP agent.
3 . The SoC of claim 1 , wherein the negotiation involves the interconnect generating a plurality of inquiries for the IP agent each requesting an “awake” status of the IP agent, the plurality of inquiries sent at periodic intervals respectively.
4 . The SoC of claim 1 , wherein the negotiation involves the IP agent generating a positive response in reply to an inquiry from the interconnect requesting an “awake” status of the IP agent, the positive response generated when the IP agent awakens and is transaction ready.
5 . The SoC of claim 1 , wherein the negotiation involves an exchange of credits available at the interconnect and at the IP agent respectively.
6 . The SoC of claim 1 , wherein the negotiation involves the interconnect and the IP agent sharing security information.
7 . The SoC of claim 1 , wherein the negotiation involves the interconnect sharing a number of virtual channels associated with a link coupling the interconnect and the IP agent.
8 . The SoC of claim 1 , wherein, after the negotiation is complete, availability of the IP agent is made known to elements coupled to the interconnect including a system controller.
9 . The SoC of claim 1 , further comprising a link coupled between the interconnect and the IP agent, the negotiation conducted between the interconnect and the IP agent over the link.
10 . The SoC of claim 9 , wherein a plurality of virtual channels are associated with the link.
11 . The SoC of claim 1 , wherein the negotiation is conducted using link-level information that is transmitted over a link between the interconnect and the IP agent.
12 . The SoC of claim 11 , wherein the link-level information is conveyed in one or more control packets that is/are transmitted over the link between the interconnect and the IP.
13 . The SoC of claim 12 , wherein the one or more control packets are transmitted over the link between the interconnect and the IP agent and are not forwarded to another destination.
14 . The SoC of claim 1 , wherein the reset manager initiates the reset of the IP agent in response to a reset trigger event.
15 . The SoC of claim 14 , wherein the reset trigger event includes one of the following:
power up of the SoC;
the IP agent has malfunctioned; or
the IP agent is emerging from a low power mode.
16 . The SoC of claim 1 , further comprising a quiesce manager for placing a link between the interconnect and the IP agent into a quiescent state.
17 . The SoC of claim 16 , wherein the quiesce manager is configured to place the link in the quiescent state after all outstanding transactions generated by the IP agent are complete.
18 . The SoC of claim 17 , wherein the quiesce manager is configured to prevent the IP agent from generating new transactions while waiting for the outstanding transactions to complete.
19 . The SoC of claim 17 , wherein the quiesce manager is configured to place the link in the quiescent state before the reset manager initiates the reset of the IP agent.
20 . A System on a Chip (SoC), comprising:
an interconnect;
a plurality of IP agents; and
a reset manager arranged to implement a reset of the plurality of IP agents, the reset of each of the plurality of IP agents involving individual negotiations between the interconnect and each of the plurality of IP agents respectively, the individual negotiations resulting in each of the IP agents becoming transaction ready respectively.
21 . The SoC of claim 20 , wherein each of the plurality of IP agents uses its own reset routine.
22 . The SoC of claim 20 , wherein each of the plurality of IP agents becomes transaction ready on its own time schedule respectively.
23 . The SoC of claim 20 , wherein each of the plurality of IP agents becomes transaction ready independent of the other IP agents and all the IP agents are not required to become transaction ready at the same time.
24 . The SoC of claim 20 , wherein the individual negotiations for each of the plurality of IP functions are the same regardless if the IP agents are different.
25 . The SoC of claim 20 , wherein the interconnect is further configured to operate as a proxy on behalf of at least one of the plurality of IP agents prior to the at least one IP agent becoming transaction ready.
26 . The SoC of claim 25 , wherein the interconnect operates as the proxy for the at least one IP agent prior to becoming transaction ready by generating an exception message to a source attempting to send a transaction to the at least one IP agent.