PROTOCOL LEVEL CONTROL FOR SYSTEM ON A CHIP (SOC) AGENT RESET AND POWER MANAGEMENT
A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
1 . A system on a Chip (SoC), comprising:
a plurality of IP agents; and
an interconnect in communication with the plurality of IP agents, the interconnect arranged to operate as a proxy on behalf of at least one of the plurality of IP agents when the at least one IP agent is not transaction ready.
2 . The SoC of claim 1 , wherein the at least one IP agent is not transaction ready when undergoing a reset.
3 . The SoC of claim 1 , wherein the at least one IP agent is not transaction ready while in a power down mode.
4 . The SoC of claim 1 , wherein the at least one IP agent is not transaction ready when malfunctioning.
5 . The SoC of claim 1 , wherein the interconnect acts as the proxy on behalf of the at least one IP agent by:
ascertaining when the at least one IP function is not transaction ready;
ascertaining if a source sends a transaction to the at least one IP agent while not transaction ready; and
sending an exception message to the source notifying the source that the at least one IP agent is not available.
6 . The SoC of claim 5 , wherein the source, in response to the exception message, undergoes its own response procedure for transactions sent but not delivered to a destination.
7 . The SoC of claim 1 , further comprising a reset manager for initiating a reset of the plurality of IP agents respectively.
8 . The SoC of claim 1 , wherein the interconnect is further configured to engage in individual negotiations with each of the plurality of IP agents when each of the plurality of IP agents is reset respectively.
9 . The SoC of claim 1 , wherein upon a reset of two or more of the plurality of IP agents, each of the two or more IP agents is arranged to individually reset and become transaction ready independent of the other IP agents respectively.
10 . The SoC of claim 9 , wherein each of the two or more IP agents independently become transaction ready on their own time-schedule with no requirement that the two or more IP agents become transaction ready at the same time.
11 . The SoC of claim 1 , further comprising a system controller, at least one IP agent becoming visible to the system controller when the at least one IP agent becomes transaction ready.
12 . A System on a Chip (SoC), comprising:
a plurality of IP agents:
an interconnect;
one or more links connecting the plurality of IP agents with the interconnect; and
a power manager for at least partially managing power consumption by the SoC by selectively placing at least one of the plurality of IP agents in a low power state,
wherein the interconnect acts as a proxy on behalf of the at least one IP agent when (a) in the low power state and (b) is unavailable for processing a transaction, the interconnect acting as the proxy by providing an exception message to a source attempting to send the transaction to the at least one IP agent.
13 . The SoC of claim 12 , wherein the at least one IP agent implements its own low power sequence when entering the low power state.
14 . The SoC of claim 12 , wherein the low power state includes a low power mode where the at least one IP agent remains transaction ready.
15 . The SoC of claim 14 , wherein the interconnect does not act as a proxy when the at least one IP agent is in the low power state and remains transaction ready, but adjusts settings on one of the one or more links to accommodate a lowered clock frequency and/or voltage for operating the at least one IP agent.
16 . The SoC of claim 12 , wherein the low power state includes a low power mode where the at least one IP agent is no longer transaction ready.
17 . The SoC of claim 16 , wherein the at least one IP agent retains state information when in the low power mode and is no longer transaction ready.
18 . The SoC of claim 16 , wherein the at least one IP agent does not retain state information when in the low power mode and is no longer transaction ready.
19 . The SoC of claim 12 , wherein the low power state includes a power off mode where minimal power is supplied to the at least one IP agent.
20 . The SoC of claim 16 wherein the low power state is implemented by reducing an operating clock frequency for the at least one IP agent.
21 . The SoC of claim 12 , wherein the low power state is implemented by reducing a voltage used by the at least one IP agent.
22 . The SoC of claim 12 , wherein the low power state is implemented by:
reducing an operating clock frequency for the at least one IP agent; and
reducing a supply voltage used by the at least one IP agent after reducing the operating clock frequency.