Combined secure mac and device correction using encrypted parity with multi-key domains

1. An apparatus, comprising:

a controller comprising circuitry, the controller to:

generate an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits;

apply a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits;

generate a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits;

encode the first plurality of data blocks to generate a first encoded data set;

encode the metadata block to generate a first encoded metadata block; and

store the first encoded data set and the first encoded metadata block on a memory module.

2. The apparatus of claim 1 , wherein the memory module comprises a plurality of memory devices and wherein the first encoded metadata block and the first encoded data set are each stored on a separate memory device of the plurality of memory devices.

3. The apparatus of claim 1 , the controller to:

encrypt a physical address of a memory location with a domain key to generate a domain specific product; and

truncate the domain-specific product to a desired length.

4. The apparatus of claim 1 , the controller to:

apply the domain-specific function to the first plurality of data blocks.

5. The apparatus of claim 4 , the controller to:

maintain an error data buffer table in a memory, the error data buffer table to store address information and data from the memory module that has been identified as having at least one error.

6. The apparatus of claim 5 , the controller to:

receive, from a requestor, a read request directed to access a cache memory address stored in the error data buffer table; and

forward the data associated with the cache memory address in the error data buffer table to an error code correction engine for correction.

7. The apparatus of claim 1 , the controller to:

obtain a second encoded data set and a corresponding second encoded metadata block from the memory module;

decode the second encoded set and the corresponding second encoded metadata block to generate a second modified block of parity bits;

apply the domain-specific function to the second modified block of parity bits to generate a recovered second block of parity bits;

combine the recovered second block of parity bits with a recovered first block of parity bits to generate a recovered error correction code; and

determine whether at least one error is present in the second encoded data set or corresponding second encoded metadata block based on a comparison between the error correction code and the recovered error correction code.

8. A computer-implemented method, comprising:

generating an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits;

applying a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits;

generating a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits;

encoding the first plurality of data blocks to generate a first encoded data set;

encoding the metadata block to generate a first encoded metadata block; and

store the first encoded data set and the first encoded metadata block on a memory module.

9. The computer-implemented method of claim 8 , wherein the memory module comprises a plurality of memory devices and wherein the first encoded metadata block and the first encoded data set are each stored on a separate memory device of the plurality of memory devices.

10. The computer-implemented method of claim 8 , further comprising:

encrypting a physical address of a memory location with a domain key to generate a domain-specific product; and

truncating the domain-specific product to a desired length.

11. The computer-implemented method of claim 10 , further comprising:

applying the domain-specific function to the first plurality of data blocks.

12. The computer-implemented method of claim 11 , further comprising:

obtaining a second encoded data set and a corresponding second encoded metadata block from the memory module;

decoding the second encoded set and the corresponding second encoded metadata block to generate a second modified block of parity bits;

applying the domain-specific function to the second modified block of parity bits to generate a recovered second block of parity bits;

combining the recovered second block of parity bits with a recovered first block of parity bits to generate a recovered error correction code; and

determining whether at least one error is present in the second encoded data set or corresponding second encoded metadata block based on a comparison between the error correction code and the recovered error correction code.

13. The computer-implemented method of claim 11 , further comprising:

maintaining an error data buffer table in a memory, the error data buffer table to store address information and data from the memory module that has been identified as having at least one error.

14. The computer-implemented method of claim 13 , further comprising:

receiving, from a requestor, a read request directed to access a cache memory address stored in the error data buffer table; and

forwarding the data associated with the cache memory address in the error data buffer table to an error code correction engine for correction.

15. A non-transitory computer-readable medium comprising instructions which, when executed by a processor, configure the processor to:

generate an error correction code for a memory line, the memory line comprising a first plurality of data blocks, wherein the error correction code comprises a first plurality of parity bits and a second plurality of parity bits;

apply a domain-specific function to the second plurality of parity bits to generate a modified block of parity bits;

generate a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least a portion of the modified block of parity bits;

encode the first plurality of data blocks to generate a first encoded data set;

encode the metadata block to generate a first encoded metadata block; and

store the first encoded data set and the first encoded metadata block on a memory module.

16. The non-transitory computer-readable medium of claim 15 , wherein the memory module comprises a plurality of memory devices and wherein the first encoded metadata block and the first encoded data set are each stored on a separate memory device of the plurality of memory devices.

17. The non-transitory computer-readable medium of claim 15 , wherein:

encrypt a physical address of a memory location with a domain key to generate a domain specific product; and

truncate the domain-specific product to a desired length.

18. The non-transitory computer-readable medium of claim 17 , further comprising instructions which, when executed by the processor, configure the processor to:

apply the domain-specific function to the first plurality of data blocks.

19. The non-transitory computer-readable medium of claim 18 , further comprising instructions which, when executed by the processor, configure the processor to:

obtain a second encoded data set and a corresponding second encoded metadata block from the memory module;

decode the second encoded set and the corresponding second encoded metadata block to generate a second modified block of parity bits;

apply the domain-specific function to the second modified block of parity bits to generate a recovered second block of parity bits;

combine the recovered second block of parity bits with a recovered first block of parity bits to generate a recovered error correction code; and

determine whether at least one error is present in the second encoded data set or corresponding second encoded metadata block based on a comparison between the error correction code and the recovered error correction code.

20. The non-transitory computer-readable medium of claim 19 , further comprising instructions which, when executed by the processor, configure the processor to:

maintain an error data buffer table in a memory, the error data buffer table to store address information and data from the memory module that has been identified as having at least one error.

21. The non-transitory computer-readable medium of claim 20 , further comprising instructions which, when executed by the processor, configure the processor to:

receive, from a requestor, a read request directed to access a cache memory address stored in the error data buffer table; and

forward the data associated with the cache memory address in the error data buffer table to an error code correction engine for correction.