IP Library Granted Patent US 11,769,789
Granted Patent B2
US 11,769,789 · App. 16/368,450 · Granted Sep 26, 2023

MFM capacitor with multilayered oxides and metals and processes for forming such

Inventors: Nazila Haratipour (Hillsboro, OR); Chia-Ching Lin (Portland, OR); Sou-Chi Chang (Portland, OR); Ashish Verma Penumatcha (Hillsboro, OR); Owen Loh (Portland, OR); Mengcheng Lu (Portland, OR); Seung Hoon Sung (Portland, OR); Ian A. Young (Portland, OR); Uygar Avci (Portland, OR); Jack T. Kavalieros (Portland, OR)
Assignee: Intel Corporation
H01L28/56H01G4/012H01G4/30H01L23/5226H10B51/00
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Quick Facts
Patent No.
US 11,769,789
App. No.
16/368,450
Granted
Sep 26, 2023
Kind
B2
Abstract

A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

Claims (52)

1. A capacitor, comprising:

a first metal layer;

a second metal layer on the first metal layer, the second metal layer including a first non-reactive barrier metal;

a ferroelectric layer on the second metal layer;

a third metal layer on the ferroelectric layer, the third metal layer including a second non-reactive barrier metal; and

a fourth metal layer on the third metal layer, wherein the ferroelectric layer extends laterally beyond the third metal layer and the fourth metal layer, and wherein the ferroelectric layer has an uppermost surface at a same level as an uppermost surface of the third metal layer and the fourth metal layer.

2. The capacitor of claim 1 , further comprising a metal via in a first dielectric layer.

3. The capacitor of claim 2 , wherein the first metal layer is in a space in a second dielectric layer.

4. The capacitor of claim 3 , further comprising a third dielectric layer above a top surface of the ferroelectric layer.

5. The capacitor of claim 4 , further comprising a connector metal in a space in the third dielectric layer.

6. The capacitor of claim 1 , further comprising a metal fill in a space that is defined by the fourth metal layer.

7. The capacitor of claim 1 , wherein the ferroelectric layer includes ferroelectric oxide.

8. A capacitor, comprising:

an intermediate dielectric layer;

a first metal layer in a space in the intermediate dielectric layer;

a second metal layer on the first metal layer, the second metal layer including a first non-reactive barrier metal;

a ferroelectric layer on the second metal layer and extending onto a top surface of the intermediate dielectric layer;

a third metal layer on the ferroelectric layer, the third metal layer including a second non-reactive barrier metal;

a fourth metal layer on the third metal layer, wherein the ferroelectric layer extends laterally beyond the third metal layer and the fourth metal layer, and wherein the ferroelectric layer has an uppermost surface at a same level as an uppermost surface of the third metal layer and the fourth metal layer; and

a top dielectric layer above an upper surface of the ferroelectric layer and a bottom dielectric layer below the intermediate dielectric layer.

9. The capacitor of claim 8 , further comprising a metal via underneath the first metal layer.

10. The capacitor of claim 8 , further comprising a metal fill in a space that is defined by the fourth metal layer.

11. The capacitor of claim 8 , wherein the ferroelectric layer includes a ferroelectric oxide.

12. The capacitor of claim 8 , further comprising a connector metal in a space in the top dielectric layer.

13. A system, comprising:

one or more processing components; and

one or more data storage components, the data storage components including at least one capacitor, the at least one capacitor including:

a first metal layer;

a second metal layer on the first metal layer, the second metal layer including a first non-reactive barrier metal;

a ferroelectric layer on the second metal layer;

a third metal layer on the ferroelectric layer, the third metal layer including a second non-reactive barrier metal; and

a fourth metal layer on the third metal layer, wherein the ferroelectric layer extends laterally beyond the third metal layer and the fourth metal layer, and wherein the ferroelectric layer has an uppermost surface at a same level as an uppermost surface of the third metal layer and the fourth metal layer.

14. The system of claim 13 , further comprising a metal via in a first dielectric layer.

15. The system of claim 14 , wherein the first metal layer is in a space in a second dielectric layer.

16. The system of claim 15 , further comprising a third dielectric layer above a top surface of the ferroelectric layer.

17. The system of claim 16 , further comprising a connector metal in a space in the third dielectric layer.

18. The system of claim 13 , further comprising a metal fill in a space that is defined by the fourth metal layer.

19. The system of claim 13 , wherein the ferroelectric layer includes a ferroelectric oxide.

20. A method, comprising:

forming a first dielectric layer;

forming a metal via in the first dielectric layer;

forming a second dielectric layer;

forming a first space in the second dielectric layer;

forming a first metal layer in the first space;

forming a first non-reactive barrier layer on the first metal layer;

forming a ferroelectric layer on the first non-reactive barrier layer;

forming a second non-reactive barrier layer on the ferroelectric layer; and

forming a second metal layer on the second non-reactive barrier layer, wherein the ferroelectric layer extends laterally beyond the second non-reactive barrier layer and the second metal layer, and wherein the ferroelectric layer has an uppermost surface at a same level as an uppermost surface of the second non-reactive barrier layer and the second metal layer.

21. The method of claim 20 , wherein the forming the ferroelectric layer includes forming the ferroelectric layer to extend onto a surface of the second dielectric layer.

22. The method of claim 20 , further comprising forming a metal fill in a space formed by the second metal layer.

23. The method of claim 20 further comprising forming a third dielectric layer above the second dielectric layer.

24. The method of claim 23 further comprising forming a space in the third dielectric layer and forming a connector metal in the space in the third dielectric layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072850/0914 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2020
From: HARATIPOUR, NAZILA; LIN, CHIA-CHING; CHANG, SOU-CHI; PENUMATCHA, ASHISH VERMA; LOH, OWEN; LU, MENGCHENG; SUNG, SEUNG HOON; YOUNG, IAN A.; AVCI, UYGAR; KAVALIEROS, JACK T.
To: INTEL CORPORATION
Reel/Frame 051573/0816 →
Continuity (1)
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