Divider circuit for parallel charging

1. A battery charging circuit, comprising:

a low dropout regulator (LDO) for providing a voltage to a battery;

a switch mode charger, coupled between the LDO and the battery, for feeding a first current to charge the battery; and

a capacitor divider, coupled between the LDO and the battery, in parallel to the switch mode charger, for dividing the voltage outputted from the LDO by an integer factor and feeding a second current to charge the battery, wherein the second current is equal to the first current times the integer factor.

2. The battery charging circuit of claim 1 , wherein the capacitor divider comprises:

a first transistor switch that receives the voltage outputted from the LDO and is serially connected to a second transistor switch via a first connecting node;

the second transistor serially connected to a third transistor switch via a second connecting node;

the third transistor switch serially connected to a fourth transistor switch via a third connecting node; and

the fourth transistor switch being connected to ground.

3. The battery charging circuit of claim 2 , wherein the first transistor switch and the third transistor switch are controlled by a same gate voltage, and the second transistor switch and the fourth transistor switch are controlled by a reverse of the same gate voltage.

4. The battery charging circuit of claim 3 , wherein the capacitor divider further comprises:

a first capacitor coupled between the first connecting node and the third connecting node; and

a second capacitor coupled between the second connecting node and the ground.

5. The battery charging circuit of claim 4 , wherein:

when the same gate voltage that controls both the first and the third transistor switches is set as a first value during a first part of a cycle:

the first transistor switch and the third transistor switch are off,

the second transistor switch and the fourth transistor switch are on, and

the third connecting node outputs a voltage level of zero; and

when the same gate voltage that controls both the first and the third transistor switches is set as a second value during a second part of the cycle:

the first transistor switch and the third transistor switch are on,

the second transistor switch and the fourth transistor switch are off, and

the third connecting node outputs the voltage level equivalent to a ratio of the voltage outputted from the LDO.

6. The battery charging circuit of claim 5 , wherein the third connecting node outputs, over a number of cycles, an average voltage level substantially similar to the voltage outputted from the LDO divided by the integer factor.

7. The battery charging circuit of claim 5 , wherein the first connecting node outputs, over a number of cycles, an average voltage level substantially similar to three quarters of the voltage outputted from the LDO.

8. The battery charging circuit of claim 4 , further comprising:

an inductor coupled between the third connecting node and the battery.

9. The battery charging circuit of claim 8 , wherein:

when the switch mode charger is turned on and the capacitor divider is turned off, the inductor passes no current from the third connecting node to the battery.

10. The battery charging circuit of claim 8 , wherein:

When the switch mode charger is turned off and the capacitor divider is turned on, the inductor passes, over a number of cycles, a current substantially similar to an average current fed to the capacitor divider from the LDO times by the integer factor, from the third connecting node to the battery.

11. A method for regulating a charging voltage for a battery charging circuit, comprising:

receiving, from a low dropout regulator (LDO), a voltage for charging a battery;

determining whether a switch mode charger coupled between the LDO and the battery is switched on;

when the switch mode charger is on:

feeding, from the LDO, a first current through the switch mode charger to charge the battery; and

when the switch mode charger is off:

dividing, by a capacitor divider coupled between the LDO and the battery, the voltage by integer factor, and

feeding a second current from the capacitor divider to the battery, wherein the second current is equal to the first current times the integer factor.

12. The method of claim 11 , wherein the dividing, by a capacitor divider coupled between the LDO and the battery, the voltage by the integer factor comprises:

feeding, by a controller, a gate voltage to a first transistor switch that receives the voltage outputted from the LDO,

wherein the first transistor switch is serially connected to a second transistor switch via a first connecting node, and the second transistor is serially connected to a third transistor switch via a second connecting node;

feeding the same gate voltage to the third transistor switch,

wherein the third transistor switch serially connected to a fourth transistor switch via a third connecting node; and

feeding a reverse of the gate voltage to both the second transistor switch and the fourth transistor switch,

wherein the fourth transistor switch is connected to ground.

13. The method of claim 12 , further comprising:

turning, by setting the gate voltage as a first value during a first part of a cycle, the first transistor switch and the third transistor switch on, and the second transistor switch and the fourth transistor switch off;

feeding a current outputted from the LDO to a first capacitor coupled between the first connecting node and the third connecting node, and a second capacitor coupled between the second connecting node and the ground;

outputting, at the third connecting node a voltage level of zero equivalent to a ratio of the voltage outputted from the LDO.

14. The method of claim 12 , further comprising:

turning, by setting the gate voltage as a second value during a second part of the cycle, the first transistor switch and the third transistor switch off, and the second transistor switch and the fourth transistor switch on; and

outputting, at the third connecting node a voltage level equivalent of zero.

15. The method of claim 12 , further comprising:

outputting, over a number of cycles, at the third connecting node, an average voltage level substantially similar to the voltage outputted from the LDO divided by the integer factor; and

passing, over the number of cycles, through an inductor coupled between the third connecting point and the battery, the current substantially similar to an average current outputted from the LDO times the integer factor.

16. A system for regulating a charging voltage for a battery charging circuit, comprising:

means for receiving, from a low dropout regulator (LDO), a voltage for charging a battery;

means for determining whether a switch mode charger coupled between the LDO and the battery is switched on;

means for when the switch mode charger is on, feeding, from the LDO, a first current through the switch mode charger to charge the battery; and

means for when the switch mode charger is off:

dividing, by a capacitor divider coupled between the LDO and the battery, the voltage by integer factor, and

feeding a second current from the capacitor divider to the battery, wherein the second current is equal to the first current times the integer factor.

17. The system of claim 16 , wherein the means for dividing, by a capacitor divider coupled between the LDO and the battery, the voltage by the integer factor comprises:

means for feeding, by a controller, a gate voltage to a first transistor switch that receives the voltage outputted from the LDO,

wherein the first transistor switch is serially connected to a second transistor switch via a first connecting node, and the second transistor is serially connected to a third transistor switch via a second connecting node;

means for feeding the same gate voltage to the third transistor switch,

wherein the third transistor switch serially connected to a fourth transistor switch via a third connecting node; and

means for feeding a reverse of the gate voltage to both the second transistor switch and the fourth transistor switch,

wherein the fourth transistor switch is connected to ground.

18. The system of claim 17 , further comprising:

means for turning, by setting the gate voltage as a first value during a first part of a cycle, the first transistor switch and the third transistor switch on, and the second transistor switch and the fourth transistor switch off;

means for feeding a current outputted from the LDO to a first capacitor coupled between the first connecting node and the third connecting node, and a second capacitor coupled between the second connecting node and the ground;

means for outputting, at the third connecting node a voltage level of zero equivalent to a ratio of the voltage outputted from the LDO.

19. The system of claim 18 , further comprising:

means for turning, by setting the gate voltage as a second value during a second part of the cycle, the first transistor switch and the third transistor switch off, and the second transistor switch and the fourth transistor switch on; and

means for outputting, at the third connecting node a voltage level equivalent of zero.

20. The system of claim 19 , further comprising:

means for outputting, over a number of cycles, at the third connecting node, an average voltage level substantially similar to the voltage outputted from the LDO divided by the integer factor; and

means for passing, over the number of cycles, through an inductor coupled between the third connecting point and the battery, the current substantially similar to an average current outputted from the LDO time the integer factor.