Performing soft throttling and hard throttling in a processor

1. A processor comprising:

a plurality of processing engines to execute instructions; and

power limit logic to:

in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine;

determine a ratio of the soft throttling events to the hard throttling events;

compare the determined ratio to a desired goal; and

adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal.

2. The processor of claim 1 , the power limit logic to:

detect a first power spike based on a determination that a level of electrical current provided to the first processing engine exceeds a threshold value;

in response to the first power spike, perform soft throttling in the first processing engine;

after completion of the soft throttling, determine whether the first power spike was resolved by the soft throttling; and

in response to a determination that the first power spike was not resolved by the soft throttling, perform hard throttling in the first processing engine.

3. The processor of claim 2 , wherein the soft throttling comprises a first reduction of an operating frequency of the first processing engine, wherein the hard throttling comprises a second reduction of the operating frequency of the first processing engine, and wherein the second reduction is relatively larger than the first reduction.

4. The processor of claim 3 , wherein the hard throttling further comprises blocking of instruction execution in the first processing engine.

5. The processor of claim 1 , the power limit logic to:

in response to a determination that the determined ratio is less than the desired goal, increase a throttling level of the soft throttling.

6. The processor of claim 5 , the power limit logic to:

in response to a determination that the determined ratio is greater than the desired goal, decrease the throttling level of the soft throttling.

7. The processor of claim 1 , the power limit logic to:

model a plurality of ratios of soft throttling events to hard throttling events;

determine a particular ratio of the plurality of ratios that is associated with a minimum performance impact; and

set the particular ratio as the desired goal.

8. The processor of claim 1 , further comprising a power control unit, wherein the power limit logic sends a request to the power control unit for a specific reduced operating frequency for the first processing engine.

9. A method, comprising:

performing a number of soft throttling events and a number of hard throttling events in a first core of a plurality of cores in a processor;

determining a ratio of the soft throttling events to the hard throttling events in the core;

determining whether the determined ratio matches a desired goal; and

in response to a determination that the determined ratio does not match the desired goal, adjusting at least one throttling parameter of the first core.

10. The method of claim 9 , further comprising:

detecting a first power spike based on a determination that a level of electrical current provided to the first core exceeds a threshold value;

in response to the first power spike, performing soft throttling in the first core;

upon completion of the soft throttling, determining whether the first power spike was resolved by the soft throttling; and

in response to a determination that the first power spike was not resolved by the soft throttling, performing hard throttling in the first core.

11. The method of claim 10 , wherein the soft throttling comprises a first reduction of an operating frequency of the first processing engine, wherein the hard throttling comprises a second reduction of the operating frequency of the first processing engine, and wherein the second reduction is relatively larger than the first reduction.

12. The method of claim 11 , wherein the hard throttling further comprises blocking of instruction execution in the first processing engine.

13. The method of claim 9 , comprising:

in response to a determination that the determined ratio is less than the desired goal, increasing a throttling level of the soft throttling.

14. The method of claim 9 , comprising:

in response to a determination that the determined ratio is greater than the desired goal, decreasing the throttling level of the soft throttling.

15. The method of claim 9 , comprising:

modeling a plurality of ratios of soft throttling events to hard throttling events;

determining a particular ratio of the plurality of ratios that is associated with a minimum performance impact; and

setting the particular ratio as the desired goal.

16. A system comprising:

a processor comprising a plurality of cores to execute instructions, wherein a first core comprises a power limit circuit to:

perform a number of soft throttling events and a number of hard throttling events in the first core;

determine a ratio of the soft throttling events to the hard throttling events over a first time period;

determine whether the determined ratio matches a desired goal; and

adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal; and

a system memory coupled to the processor.

17. The system of claim 16 , the power limit circuit to:

detect a first power spike based on a determination that a level of electrical current provided to the first core exceeds a threshold value;

in response to the first power spike, perform soft throttling in the first core;

after completion of the soft throttling, determine whether the first power spike was resolved by the soft throttling; and

in response to a determination that the first power spike has not been resolved by the soft throttling, perform hard throttling in the first core.

18. The system of claim 17 , wherein the soft throttling comprises a first reduction of an operating frequency of the first core, wherein the hard throttling comprises a second reduction of the operating frequency of the first core, and wherein the second reduction is relatively larger than the first reduction.

19. The system of claim 18 , the power limit circuit to:

in response to a determination that the determined ratio is less than the desired goal, increase a throttling level of the soft throttling in the first core.

20. The system of claim 16 , the power limit circuit to:

in response to a determination that the determined ratio is greater than the desired goal, decrease the throttling level of the soft throttling in the first core.