IP Library Granted Patent US 11,901,400
Granted Patent B2
US 11,901,400 · App. 16/369,737 · Granted Feb 13, 2024

MFM capacitor and process for forming such

Inventors: Nazila Haratipour (Hillsboro, OR); Chia-Ching Lin (Portland, OR); Sou-Chi Chang (Portland, OR); Ashish Verma Penumatcha (Hillsboro, OR); Owen Loh (Portland, OR); Mengcheng Lu (Portland, OR); Seung Hoon Sung (Portland, OR); Ian A. Young (Portland, OR); Uygar Avci (Portland, OR); Jack T. Kavalieros (Portland, OR)
Assignee: Intel Corporation
H01L28/56H01G4/012H01G4/30H01L23/5226H10B51/00
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Quick Facts
Patent No.
US 11,901,400
App. No.
16/369,737
Granted
Feb 13, 2024
Kind
B2
Abstract

A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Claims (33)

1. A capacitor, comprising:

a first metal layer in a trench in a dielectric layer, the first metal layer having an uppermost surface at a same level as an uppermost surface of the dielectric layer;

a seed layer on the first metal layer, the seed layer including a polar phase crystalline structure;

a ferroelectric layer on the seed layer, the ferroelectric layer along and in contact with the uppermost surface of the dielectric layer; and

a second metal layer on the ferroelectric layer, wherein the ferroelectric layer extends laterally beyond the second metal layer and laterally beyond the first metal layer, and wherein the ferroelectric layer has a bottommost surface below the uppermost surface of the first metal layer.

2. The capacitor of claim 1 , further comprising a metal via in a second dielectric layer.

3. The capacitor of claim 1 , wherein the seed layer is a templating layer.

4. The capacitor of claim 1 , wherein the seed layer has a predetermined lattice constant.

5. The capacitor of claim 1 , wherein the ferroelectric layer includes a ferroelectric oxide.

6. The capacitor of claim 1 , wherein the capacitor is a metal-ferroelectric-metal (MFM) capacitor.

7. The capacitor of claim 1 , wherein the first metal layer is a conformal metal layer.

8. A capacitor, comprising:

a first metal layer in an opening in a first dielectric layer, the first metal layer having an uppermost surface at a same level as an uppermost surface of the first dielectric layer;

a ferroelectric layer on the first metal layer, the ferroelectric layer along and in contact with the uppermost surface of the first dielectric layer;

a second metal layer on the ferroelectric layer; and

a third metal layer on the second metal layer, wherein the thickness of the third metal layer is greater than the thickness of the second metal layer, wherein the ferroelectric layer extends laterally beyond the second metal layer and the third metal layer and laterally beyond the first metal layer, and wherein the ferroelectric layer has a bottommost surface below the uppermost surface of the first metal layer.

9. The capacitor of claim 8 , wherein the second metal layer has a higher resistivity than the third metal layer.

10. The capacitor of claim 8 , wherein the second metal layer has a smaller grain size than the third metal layer.

11. The capacitor of claim 8 , wherein the ferroelectric layer includes a ferroelectric oxide.

12. The capacitor of claim 8 , wherein the first metal layer is a conformal metal layer.

13. The capacitor of claim 8 , wherein the capacitor is an MFM capacitor.

14. The capacitor of claim 8 , further comprising a second dielectric layer under the first dielectric layer; and a metal via in the second dielectric layer.

15. A system, comprising:

one or more processing components; and

one or more data storage components, the data storage components including at least one capacitor, the at least one capacitor including:

a first metal layerin a trench in a dielectric layer, the first metal layer having an uppermost surface at a same level as an uppermost surface of the dielectric layer;

a seed layer on the first metal layer, the seed layer including a polar phase crystalline structure;

a ferroelectric layer on the seed layer, the ferroelectric layer along and in contact with the uppermost surface of the dielectric layer; and

a second metal layer on the ferroelectric layer, wherein the ferroelectric layer extends laterally beyond the second metal layer and laterally beyond the first metal layer, and wherein the ferroelectric layer has a bottommost surface below the uppermost surface of the first metal layer.

16. The system of claim 15 , further comprising a metal via in a second dielectric layer.

17. The system of claim 15 , wherein the seed layer is a templating layer.

18. The system of claim 15 , wherein the seed layer has a predetermined lattice constant.

19. The system of claim 15 , wherein the ferroelectric layer includes a ferroelectric oxide.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072850/0914 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2020
From: HARATIPOUR, NAZILA; LIN, CHIA-CHING; CHANG, SOU-CHI; PENUMATCHA, ASHISH VERMA; LOH, OWEN; LU, MENGCHENG; SUNG, SEUNG HOON; YOUNG, IAN A.; AVCI, UYGAR; KAVALIEROS, JACK T.
To: INTEL CORPORATION
Reel/Frame 051491/0958 →
Continuity (1)
Related Publication 20200312950A1 · Oct 1, 2020