Semiconductor device and manufacturing method thereof
A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.
1. A semiconductor device comprising:
a fin structure disposed over a substrate, the fin structure including an upper layer being exposed from an isolation insulating layer;
a gate structure disposed over part of the upper layer of the fin structure; and
a source which includes the upper layer of the fin structure not covered by the gate structure, wherein:
the upper layer of the fin structure of the source is covered by a crystal semiconductor layer,
the crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element,
the silicide layer is covered by a first metal layer, and
a second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer and in direct contact with the isolation insulating layer.
2. The semiconductor device of claim 1 , wherein the first metal layer is divided by a third metal layer made of the first metal element.
3. The semiconductor device of claim 2 , wherein the third metal layer is disposed at a level of a top of the fin structure of the source.
4. The semiconductor device of claim 1 , wherein the first metal element is at least one of Ni, Ti and Co.
5. The semiconductor device of claim 4 , wherein the first metal layer is made of W.
6. The semiconductor device of claim 1 , wherein the crystal semiconductor layer is doped with impurities at an amount of 2×10 20 cm −3 to 1×10 21 cm −3 .
7. The semiconductor device of claim 6 , wherein the impurities are phosphorous.
8. The semiconductor device of claim 1 , wherein the first metal element has a lower silicide formation temperature than a metal element of the first metal layer.
9. The semiconductor device of claim 1 , wherein a thickness of the second metal layer is in a range from 0.5 nm to 3 nm.
10. The semiconductor device of claim 1 , wherein:
the silicide layer includes a first silicide layer formed by Si and the first metal element and a second silicide layer formed by Si and a second metal element of the first metal layer.
11. The semiconductor device of claim 10 , wherein the first metal element is at least one of Ni, Ti and Co.
12. The semiconductor device of claim 11 , wherein the second metal element is W.
13. The semiconductor device of claim 10 , wherein the crystal semiconductor layer is doped with impurities at an amount of 2×10 20 cm −3 to 1×10 21 cm −3 .
14. The semiconductor device of claim 13 , wherein the impurities are phosphorous.
15. The semiconductor device of claim 10 , wherein the first metal element has a lower silicide formation temperature than a metal element of the first metal layer.
16. The semiconductor device of claim 10 , wherein a thickness of the second metal layer is in a range from 0.5 nm to 3 nm.
17. A semiconductor device comprising:
a first fin structure and a second fin structure both disposed over a substrate, each of the first and second fin structures including an upper layer being exposed from an isolation insulating layer, wherein:
each of the first and second fin structures includes a source region and a drain region,
the upper layer of each of the first and second fin structures at each of the source region and the drain region is covered by a crystal semiconductor layer,
the crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element,
the silicide layer is covered by a first metal layer,
a second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer, and
the first metal layer is divided by a third metal layer made of the first metal element.
18. The semiconductor device of claim 17 , wherein the silicide layer disposed over the first fin structure is discontinuous from the silicide layer disposed over the second fin structure.
19. The semiconductor device of claim 18 , wherein the second metal layer is disposed between the silicide layer disposed over the first fin structure and the silicide layer disposed over the second fin structure.
20. A semiconductor device comprising:
a first fin structure, a second fin structure and a third fin structure, all disposed over a substrate, each of the first to third fin structures including an upper layer being exposed from an isolation insulating layer, wherein:
each of the first to third fin structures includes a source region and a drain region,
the upper layer of each of the first to third fin structures at each of the source region and the drain region is covered by a crystal semiconductor layer,
the crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element,
the silicide layer is covered by a first metal layer,
a second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer, and
the first metal layer is divided by a third metal layer made of the first metal element.