Nonvolatile memory device, operation method of the nonvolatile memory device, and operation method of memory controller controlling the nonvolatile memory device

1. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory cells connected to a plurality of word lines;

a control logic circuit configured to receive a first sequential read command and a second sequential read command following the first sequential read command from outside the nonvolatile memory device;

a sequential address generator configured to generate a plurality of sequential addresses based on sequential read information received from the outside of the nonvolatile memory device, under control of the control logic circuit receiving the first and second sequential read commands;

an address decoder connected to the memory cell array through the plurality of word lines, and configured to sequentially select a plurality of pages in at least one word line, which correspond to the plurality of sequential addresses, from among the plurality of word lines, under control of the control logic circuit receiving the first and second sequential read commands;

a page buffer circuit connected to the memory cell array through a plurality of bit lines, and configured to prepare a plurality of sequential data from memory cells connected to the selected pages by the address decoder, under control of the control logic circuit receiving the sequential first and second read commands; and

an input/output circuit configured to continuously output the plurality of sequential data from the page buffer circuit to the outside of the nonvolatile memory device through data lines, under control of the control logic circuit,

wherein the control logic circuit is configured to receive the first sequential read command during a first command input interval, and to receive the second sequential read command during a second command input interval following the first command input interval,

wherein the sequential address generator is configured to receive the sequential read information during an address input interval between the first command input interval and the second command input interval, and

wherein after the second command input interval, the input/output circuit continuously outputs the plurality of sequential data from the selected pages based on the sequential read information.

2. The nonvolatile memory device of claim 1 , wherein the input/output circuit is configured to continuously output the plurality of sequential data without receiving an additional command or an address from the outside of the nonvolatile memory device at the control logic circuit.

3. The nonvolatile memory device of claim 1 , wherein the sequential address generator is configured to receive the sequential read information through the data lines in synchronization with a rising edge of a write enable signal received from the outside of the nonvolatile memory device, during the address input interval, where a command latch enable signal from the outside of the nonvolatile memory device is logical low and an address latch enable signal from the outside of the nonvolatile memory device is logical high.

4. The nonvolatile memory device of claim 3 , wherein the control logic circuit is configured to receive the sequential read information within 5 periods of the write enable signal.

5. The nonvolatile memory device of claim 1 , wherein the plurality of sequential data are continuously output in synchronization with a rising edge and a falling edge of a data strobe signal based on a read enable signal received from the outside of the nonvolatile memory device.

6. The nonvolatile memory device of claim 1 , wherein the sequential read information includes information about a sequential read mode, information about a size of each of the plurality of sequential data, and information about the number of the plurality of sequential data.

7. The nonvolatile memory device of claim 6 , further comprising:

a storage circuit configured to store a look-up table including correspondence information of the sequential read mode of the sequential read information and a sequential address generation policy.

8. The nonvolatile memory device of claim 7 , wherein the sequential address generator is configured to generate the plurality of sequential addresses based on the sequential address generation policy corresponding to the sequential read mode received from the outside of the nonvolatile memory device.

9. The nonvolatile memory device of claim 7 , wherein the look-up table is configured to be updated in response to a set feature command received from the outside of the nonvolatile memory device.

10. The nonvolatile memory device of claim 1 , wherein the control logic circuit is further configured to receive a suspend signal received from the outside of the nonvolatile memory device while the plurality of sequential data are continuously output, and to suspend an output operation associated with the plurality of sequential data in response to the received suspend signal.

11. An operation method of a nonvolatile memory device, the method comprising:

receiving a first sequential read command from outside the nonvolatile memory device through data lines during a first command input interval;

receiving sequential read information from the outside of the nonvolatile memory device through the data lines during an address input interval following the first command input interval;

receiving a second sequential read command from the outside of the nonvolatile memory device through the data lines during a second command input interval following the address input interval; and

continuously outputting a plurality of sequential data based on the sequential read information after the second command input interval,

wherein the plurality of sequential data correspond to a plurality of physical pages, respectively.

12. The method of claim 11 , further comprising:

during the address input interval, receiving a command latch enable signal of logical low received from the outside of the nonvolatile memory device, and an address latch enable signal of logical high received from the outside of the nonvolatile memory device,

wherein the sequential read information is received in synchronization with a rising edge of a write enable signal received from the outside of the nonvolatile memory device.

13. The method of claim 11 , further comprising:

during the first command input interval and the second command input interval, receiving a command latch enable signal of logical high received from the outside of the nonvolatile memory device, and an address latch enable signal of logical low received from the outside of the nonvolatile memory device,

wherein the first sequential read command and the second sequential read command are received in synchronization with a rising edge of a write enable signal received from the outside of the nonvolatile memory device.

14. The method of claim 11 , wherein the plurality of sequential data are continuously output to the outside of the nonvolatile memory device in synchronization with a data strobe signal toggling based on a read enable signal received from the outside of the nonvolatile memory device.

15. The method of claim 11 , wherein, until the plurality of sequential data are completely output, an additional command or an address is not received by the nonvolatile memory device from the outside of the nonvolatile memory device.

16. An operation method of a memory controller which controls a nonvolatile memory device including a plurality of pages, the method comprising:

transmitting a first sequential read command to the nonvolatile memory device through data lines during a first command input interval;

transmitting sequential read information to the nonvolatile memory device through the data lines during an address input interval following the first command input interval;

transmitting a second sequential read command to the nonvolatile memory device through the data lines during a second command input interval following the address input interval; and

after the second command input interval, providing a read enable signal to the nonvolatile memory device to continuously receive a plurality of sequential data from selected pages from among the plurality of pages of the nonvolatile memory device.

17. The method of claim 16 , further comprising:

during the first and second command input intervals, transmitting a command latch enable signal of logical high to the nonvolatile memory device, and an address latch enable signal of logical low to the nonvolatile memory device,

wherein the read enable signal is logical high, and each of the first and second sequential read commands is transmitted to the nonvolatile memory device in synchronization with a rising edge of a write enable signal.

18. The method of claim 16 , further comprising:

during the address input interval, transmitting a command latch enable signal of logical low to the nonvolatile memory device, and an address latch enable signal of logical high to the nonvolatile memory device,

wherein the read enable signal is logical high, and the sequential read information is transmitted to the nonvolatile memory device in synchronization with a rising edge of a write enable signal.

19. The method of claim 16 , wherein, after a ready/busy signal received from the nonvolatile memory device transitions to a ready state, the read enable signal is provided to the nonvolatile memory device.

20. The method of claim 16 , wherein an additional command or an address is not transmitted to the nonvolatile memory device through the data lines until the plurality of sequential data are completely received from the nonvolatile memory device.