Virtual wafer techniques for fabricating semiconductor devices
A method of fabricating semiconductor devices including epitaxially depositing a heavily doped substrate layer that is substantially free of crystalline defects on a lightly doped virtual substrate. The device regions of the semiconductor devices can be fabricated about the heavily doped substrate layer before the lightly doped virtual substrate is removed.
1. A method of fabricating a semiconductor device comprising:
depositing a heavily doped crystalline semiconductor substrate directly on a lightly doped crystalline virtual semiconductor substrate, wherein the lightly doped crystalline virtual semiconductor substrate is substantially free of crystalline defects, and the deposited heavily doped crystalline semiconductor substrate is substantially free of crystalline defects as a result of the lightly doped crystalline virtual semiconductor substrate being substantially free of crystalline defects;
forming one or more regions of one or more devices about a surface of the heavily, doped crystalline semiconductor substrate;
removing the lightly doped crystalline virtual semiconductor substrate from the heavily doped crystalline semiconductor substrate leaving the one or more regions of the one or more devices formed about the heavily doped crystalline semiconductor substrate; and
annealing the heavily doped crystalline semiconductor substrate deposited on the lightly doped crystalline virtual semiconductor substrate to reduce one or more types of defects in the heavily doped crystalline semiconductor substrate before forming the one or more regions of the one or more devices.
2. The method of fabricating the semiconductor device of claim 1 , further comprising:
thinning the heavily doped crystalline semiconductor substrate after removing the lightly doped crystalline virtual semiconductor substrate.
3. The method of fabricating the semiconductor device of claim 1 , further comprising:
forming one or more additional regions of the one or more devices about the surface of the heavily doped crystalline semiconductor substrate.
4. The method of fabricating the semiconductor device of claim 1 , further comprising:
depositing a barrier layer on the lightly doped crystalline virtual semiconductor substrate before depositing the heavily doped crystalline semiconductor substrate on the lightly doped crystalline virtual semiconductor substrate, wherein the barrier layer is configured to reduce doping diffusion from the heavily doped crystalline semiconductor substrate to the lightly doped crystalline virtual semiconductor substrate.
5. A method of fabricating a semiconductor device comprising:
epitaxially depositing a heavily n-doped semiconductor substrate layer directly on a tightly n-doped virtual semiconductor substrate, wherein the lightly n-doped virtual semiconductor substrate is substantially free of crystalline defects and the epitaxially deposited heavily n-doped semiconductor substrate layer is substantially free of crystalline defects as a result of the lightly n-doped virtual semiconductor substrate being substantially free of crystalline defects;
forming one or more regions of one or more devices about a first surface of the heavily n-doped semiconductor substrate layer; and
removing the lightly n-doped virtual semiconductor substrate from the heavily n-doped semiconductor substrate layer.
6. The method of fabricating the semiconductor device of claim 5 , wherein forming the one or more regions of the one or more devices comprises:
forming a plurality of gate trenches in the heavily n-doped semiconductor substrate layer;
forming a plurality of gate dielectric regions in the plurality of gate trenches;
forming a plurality of gate regions in the plurality of gate trenches, wherein the plurality of gate dielectric regions are disposed between the heavily n-doped semiconductor substrate layer and the plurality of gate regions;
forming a plurality of p-doped body regions in a portion of the heavily n-doped substrate layer opposite the lightly n-doped virtual semiconductor substrate; and
forming a plurality of n-doped source regions in a portion of the plurality of p-doped body regions opposite the heavily n-doped semiconductor substrate layer.
7. The method of fabricating the semiconductor device of claim 6 , wherein forming the one or more regions of the one or more devices further comprises:
forming a plurality of source-body contacts coupled to the plurality of n-doped source regions and the plurality of p-doped body regions.
8. The method of fabricating the semiconductor device of claim 5 , wherein:
the lightly n-doped virtual semiconductor substrate comprises silicon(Si) lightly doped with phosphorous (P); and
the heavily n-doped semiconductor substrate layer comprises silicon heavily doped with phosphorous.
9. The method of fabricating the semiconductor device of claim 8 , further comprising:
depositing a barrier layer including arsenic (As) on the lightly n-doped virtual semiconductor substrate before epitaxially depositing the heavily n-doped semiconductor substrate layer.
10. The method of fabricating the semiconductor device of claim 8 , wherein the lightly n-doped semiconductor substrate is removed by a back grinding and polishing process.
11. The method of fabricating the semiconductor device of claim 10 , further comprising:
thinning the heavily n-doped semiconductor substrate layer about a surface opposite the one or more regions of the one or more devices.
12. The method of fabricating the semiconductor device of claim 11 , wherein the heavily n-doped semiconductor substrate layer is thinned by a back grinding and polishing process.
13. The method of fabricating the semiconductor device of claim 5 , further comprising:
annealing the heavily n-doped semiconductor substrate layer deposited on the lightly n-doped virtual semiconductor substrate to reduce one or more types of defects in the heavily n-doped semiconductor substrate layer.
14. A method of fabricating a semiconductor device comprising:
depositing a buffer layer on a crystalline virtual semiconductor substrate, wherein the crystalline virtual semiconductor substrate is substantially free of crystalline defects, wherein the buffer layer is not formed from the crystalline virtual semiconductor substrate;
epitaxially depositing a heavily doped crystalline semiconductor substrate on the buffer layer opposite the crystalline virtual semiconductor substrate, wherein the buffer layer is configured to prevent propagation of crystalline defects from the crystalline virtual semiconductor substrate into the heavily doped epitaxially deposited crystalline semiconductor substrate; and
forming one or more regions of one or more devices about a surface of the heavily doped epitaxially deposited crystalline semiconductor substrate.
15. The method of fabricating the semiconductor device of claim 14 , further comprising:
removing the crystalline virtual semiconductor substrate from the buffer layer leaving the one or more regions of the one or more devices formed about the surface of the heavily doped crystalline semiconductor substrate.
16. The method of fabricating the semiconductor device of claim 15 , further comprising:
removing the buffer layer from the heavily doped crystalline semiconductor substrate.
17. The method of fabricating the semiconductor device of claim 16 , further comprising:
thinning the heavily doped crystalline semiconductor substrate after removing the buffer layer.
18. The method of fabricating the semiconductor device of claim 14 , wherein depositing the buffer layer comprises epitaxially depositing a semiconductor heavily doped with arsenic (As) or phosphorous (P).