Magnetic tunneling junction (MTJ) element with an amorphous buffer layer and its fabrication process

1. A semiconductor device, comprising:

a bottom electrode disposed over a semiconductor substrate, the bottom electrode including a diffusive species;

a conductive seed layer comprising an amorphous, non-magnetic material disposed over the bottom electrode;

a magnetic tunnel junction (MTJ) stack disposed over the conductive seed layer; and

a buffer layer separating the conductive seed layer and the bottom electrode, wherein the buffer layer is configured to prevent diffusion of the diffusive species from the bottom electrode to the conductive seed layer and the MTJ stack, wherein the buffer layer comprises a Co—Hf film with a Hf content ranging from 18 at % to 40 at %.

2. The semiconductor device of claim 1 , wherein the buffer layer is substantially free of the diffusive species, and wherein the diffusive species is tantalum.

3. The semiconductor device of claim 1 , wherein a thickness of the buffer layer as defined between a top surface of the buffer layer and a bottom surface of the buffer layer is between 1 nm and 10 nm.

4. The semiconductor device of claim 1 , wherein the buffer layer has a substantially flat upper surface, wherein an upper surface of the bottom electrode below the buffer layer has a substantially rough upper surface.

5. The semiconductor device of claim 1 , further comprising:

a hard bias stack disposed over the conductive seed layer;

where the MTJ stack is disposed over the hard bias stack, wherein the MTJ stack comprises a reference layer, a barrier layer over the reference layer, and a free layer over the barrier layer; and

a capping layer disposed over the MTJ stack.

6. The semiconductor device of claim 5 , further comprising:

a top electrode disposed over the capping layer;

a top electrode via disposed over the top electrode;

a conductive via disposed over the top electrode via; and

a conductive wire disposed over the conductive via.

7. The semiconductor device of claim 1 , further comprising:

an interconnect via disposed beneath the bottom electrode;

a diffusion barrier layer disposed over the interconnect via and electrically coupling an upper surface of the interconnect via to a lower surface of the bottom electrode; and

an insulator structure disposed along outer sidewalls of the diffusion barrier layer, the insulator structure having an outer perimeter that fully surrounds and is larger than an outer perimeter of the MTJ stack.

8. The semiconductor device of claim 7 , wherein outer sidewalls of the bottom electrode and outer sidewalls of the diffusion barrier layer are angled and non-perpendicular relative to an upper surface of the semiconductor substrate.

9. A magneto-resistive random-access memory (MRAM) device, comprising:

a bottom electrode disposed over an interconnect via;

a seed layer disposed over the bottom electrode;

a hard bias stack disposed over the seed layer;

a reference layer disposed over the hard bias stack;

a barrier layer disposed over the reference layer;

a free layer disposed over the barrier layer;

a capping layer disposed over the free layer; and

a buffer layer separating the bottom electrode and the seed layer, wherein the buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer, the hard bias stack, and the barrier layer, wherein the buffer layer is disposed along a bottom surface of the seed layer and directly contacts the seed layer, wherein opposing sidewalls of the buffer layer and opposing sidewalls of the seed layer are aligned and non-perpendicular relative to a top surface of the bottom electrode, wherein the buffer layer has a substantially flat upper surface, wherein an upper surface of the bottom electrode below the buffer layer has a substantially rough upper surface.

10. The MRAM device of claim 9 , wherein the buffer layer is made from an amorphous nonmagnetic binary alloy of form X—Z, where X is iron (Fe) or cobalt (Co) and Z is hafnium (Hf), yttrium (Y), or Zirconium (Zr).

11. The MRAM device of claim 9 , wherein the seed layer is comprised of a multilayer stack, wherein the multilayer stack comprises a nickel chromium (NiCr) layer, cobalt iron boron (CoFeB) layer, magnesium (Mg) layer, and/or tantalum (Ta) layer.

12. The MRAM device of claim 9 , further comprising:

a diffusion barrier layer disposed below the bottom electrode; and

a pair of insulators disposed at outer sidewalls of the diffusion barrier layer, wherein the pair of insulators are outside of outer sidewalls of the interconnect via.

13. The MRAM device of claim 9 , wherein the substantially rough upper surface of the bottom electrode continuously extends along a bottom surface of the buffer layer.

14. A magneto-resistive random-access memory (M RAM) device, comprising:

a bottom electrode disposed over an interconnect via;

a seed layer disposed over the bottom electrode;

a hard bias stack disposed over the seed layer;

a reference layer disposed over the hard bias stack;

a barrier layer disposed over the reference layer;

a free layer disposed over the barrier layer;

a perpendicular magnetic anisotropy (PMA) protection layer disposed over the free layer; and

a buffer layer disposed along a bottom surface of the seed layer, wherein the buffer layer directly contacts the seed layer, wherein opposing sidewalls of the buffer layer are aligned with opposing sidewalls of the seed layer, and wherein the buffer layer comprises an amorphous nonmagnetic alloy with a form X—Z, where X is iron (Fe) or cobalt (Co) and Z is hafnium (Hf), yttrium (Y), or Zirconium (Zr) with a Z content ranging from 18 at % to 40 at %.

15. The MRAM device of claim 14 , wherein the seed layer comprises an amorphous material.

16. The MRAM device of claim 14 , wherein a thickness of the seed layer is greater than a thickness of the buffer layer.

17. The MRAM device of claim 14 , wherein the hard bias stack and the reference layer have a same crystalline structure and orientation.

18. The MRAM device of claim 14 , wherein the opposing sidewalls of the buffer layer are spaced laterally between outer sidewalls of the bottom electrode.

19. The MRAM device of claim 14 , wherein the hard bias stack comprises a plurality of alternating layers of a first material and a second material, wherein the first material is different from the second material.

20. The MRAM device of claim 14 , wherein the buffer layer directly contacts the bottom electrode.