Two stage command buffers to overlap IOMMU map and second tier memory reads
IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.
1. A method, comprising:
identifying a particular second tier memory address storing data;
allocating a page at a particular physical address of dynamic random access memory (DRAM);
sending a command to a storage controller, the command identifying the particular second tier memory address and the particular physical address and initiating a first stage in which the stored data is read from the particular second tier memory address into a buffer of the storage controller;
mapping the particular physical address into an input/output memory management unit (IOMMU), the mapping at least partially occurring during the first stage reading; and
editing the command to the storage controller to initiate a second stage in which the stored data is written from the storage controller buffer to the particular DRAM physical address.
2. The method of claim 1 , wherein the mapping is completed prior to completion of the first stage.
3. The method of claim 1 , wherein the command comprises a tuple having a bit designated for identifying at least one of an initiation of the first stage or an initiation of the second stage.
4. The method of claim 1 , wherein sending the command to the storage controller further comprises identifying the particular physical address.
5. The method of claim 1 , wherein editing the command to the storage controller comprises identifying the particular physical address, the particular physical address being a virtual address after the mapping into the IOMMU.
6. A system, comprising:
one or more memories; and
one or more processors in communication with the one or more memories, the one or more processors configured to:
identify a particular second tier memory address storing data;
allocate a page at a particular physical address of dynamic random access memory (DRAM);
send a command to a storage controller, the command identifying the particular second tier memory address and the particular physical address and initiating a first stage in which the stored data is read from the particular second tier memory address into a buffer of the storage controller;
map the particular physical address into an input/output memory management unit (IOMMU), the mapping at least partially occurring during the first stage reading; and
edit the command to the storage controller to initiate a second stage in which the stored data is written from the storage controller buffer to the particular DRAM physical address.
7. The system of claim 6 , wherein the one or more processor are configured to complete the mapping prior to completion of the first stage.
8. The system of claim 6 , wherein the command comprises a tuple having a bit designated for identifying at least one of an initiation of the first stage or an initiation of the second stage.
9. The system of claim 6 , wherein in sending the command to the storage controller the one or more processors are further configured to identify the particular physical address.
10. The system of claim 6 , wherein in editing the command to the storage controller the one or more processors are further configured to identify the particular physical address, the particular physical address being a virtual address after the mapping into the IOMMU.
11. A non-transitory computer-readable medium storing instructions executable by one or more processors to perform a method, comprising:
identifying a particular second tier memory address storing data;
allocating a page at a particular physical address of dynamic random access memory (DRAM);
sending a command to a storage controller, the command identifying the particular second tier memory address and the particular physical address and initiating a first stage in which the stored data is read from the particular second tier memory address into a buffer of the storage controller;
mapping the particular physical address into an input/output memory management unit (IOMMU), the mapping at least partially occurring during the first stage reading; and
editing the command to the storage controller to initiate a second stage in which the stored data is written from the storage controller buffer to the particular DRAM physical address.
12. The computer-readable medium of claim 11 , wherein the mapping is completed prior to completion of the first stage.
13. The computer-readable medium of claim 11 , wherein the command comprises a tuple having a bit designated for identifying at least one of an initiation of the first stage or an initiation of the second stage.
14. The computer-readable medium of claim 11 , wherein sending the command to the storage controller further comprises identifying the particular physical address.
15. The computer-readable medium of claim 11 , wherein editing the command to the storage controller comprises identifying the particular physical address, the particular physical address being a virtual address after the mapping into the IOMMU.