Accelerator sharing

1. A device for sharing an accelerator among a plurality of processors, the device comprising:

a local store for storing cache allocation information indicating allocation of cache lines to one of a plurality of coherent proxies; and

a cache directory for the cache lines used by the accelerator, the cache directory providing a status of the cache lines and identification information of the coherent proxies to which the cache lines are allocated,

wherein, in response to receiving an operation request, the device determines a presence of a cache line within the cache directory, determines a coherent proxy of the plurality of coherent proxies corresponding to the request based on the cache line, and communicates with the coherent proxy for the request.

2. The device of claim 1 , wherein determining the presence of the cache line further comprises:

determining the cache line is absent from the cache directory; and

identifying the operation request as a cache-miss request.

3. The device of claim 1 , wherein determining the presence of the cache line further comprises:

determining the cache line is present within the cache directory; and

identifying the operation request as a cache-hit request.

4. The device of claim 1 , wherein each coherent proxy maintains a shadow directory for cache lines allocated to that coherent proxy, the device further configured to:

in response to communication associated with the operation request, update a cache line status of a cache line within the shadow directory of the coherent proxy corresponding to the operation request.

5. The device of claim 4 , wherein the accelerator maintains a cache with a local store for storing cache allocation information, and each shadow directory includes a subset of cache lines and cache line status information of the cache of the accelerator, the subset of cache lines and cache line status information being associated with the coherent proxy maintaining the shadow directory.

6. A method for sharing an accelerator among a plurality of processors, the method comprising:

obtaining cache allocation information indicating allocation of cache lines to one of a plurality of coherent proxies;

in a cache directory for the cache lines, providing a status of the cache lines and identification information of the coherent proxies to which the cache lines are allocated;

in response to receiving an operation request, determining a presence of a cache line within the cache directory;

based on the cache line, determining a coherent proxy of the plurality of coherent proxies corresponding to the request; and

communicating with the coherent proxy for the request.

7. The method of claim 6 , wherein determining the presence of the cache line further comprises:

determining the cache line is absent from the cache directory; and

identifying the operation request as a cache-miss request.

8. The method of claim 6 , wherein determining the presence of the cache line further comprises:

determining the cache line is present within the cache directory; and

identifying the operation request as a cache-hit request.

9. The method of claim 6 , wherein each coherent proxy maintains a shadow directory for cache lines allocated to that coherent proxy, the method further comprising:

in response to communication associated with the operation request, updating a cache line status of a cache line within the shadow directory of the coherent proxy corresponding to the operation request.

10. The method of claim 9 , wherein the accelerator maintains a cache with a local store for storing cache allocation information, and each shadow directory includes a subset of cache lines and cache line status information of the cache of the accelerator, the subset of cache lines and cache line status information being associated with the coherent proxy maintaining the shadow directory.

11. A computer program product being tangibly stored on a non-transient machine-readable medium and comprising machine-executable instructions for sharing an accelerator among a plurality of processors, the instructions, when executed on a device, cause the device to perform operations comprising:

obtaining cache allocation information indicating allocation of cache lines to one of a plurality of coherent proxies;

in a cache directory for the cache lines, providing a status of the cache lines and identification information of the coherent proxies to which the cache lines are allocated;

in response to receiving an operation request, determining a presence of a cache line within the cache directory;

based on the cache line, determining a coherent proxy of the plurality of coherent proxies corresponding to the request; and

communicating with the coherent proxy for the request.

12. The computer program product of claim 11 , wherein determining the presence of the cache line further comprises:

determining the cache line is absent from the cache directory; and

identifying the operation request as a cache-miss request.

13. The computer program product of claim 11 , wherein determining the presence of the cache line further comprises:

determining the cache line is present within the cache directory; and

identifying the operation request as a cache-hit request.

14. The computer program product of claim 11 , wherein each coherent proxy maintains a shadow directory for cache lines allocated to that coherent proxy, the operations further comprising:

in response to communication associated with the operation request, updating a cache line status of a cache line within the shadow directory of the coherent proxy corresponding to the operation request.

15. The computer program product of claim 14 , wherein the accelerator maintains a cache with a local store for storing cache allocation information, and each shadow directory includes a subset of cache lines and cache line status information of the cache of the accelerator, the subset of cache lines and cache line status information being associated with the coherent proxy maintaining the shadow directory.