Granted Patent B2

US 12,632,385 · App. 18/754,079 · Granted May 19, 2026

Inventors: Simon Weishaupt (Kernen im Remstal, DE); Cedric Lichtenau (Stuttgart, DE); Simon Friedmann (Boeblingen, DE); Preetham M. Lobo (Bangalore, IN)

Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION

G06F12/0831G06F12/084G06F2212/1016

Abstract

Claims (41)

1 . A system, comprising:

a memory that stores computer executable components;

a signaling bus that is directly connected between a processor core and an accelerator; and

a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:

a selection component that selects the accelerator to execute one or more functions related to a program being executed by the processor core; and

a transmission component that transmits an address associated with a cache to the accelerator, wherein the address is transmitted within a start command from the processor core to the accelerator via the signaling bus, wherein the cache is accessible to both the processor core and the accelerator, and wherein the address is employable by the accelerator to install one or more messages in the cache via non-cached stores to communicate a running state of the accelerator to the processor core during execution of the one or more functions.

2 . The system of claim 1 , wherein the start command is transmitted from the processor core to the accelerator via a sideband signaling mechanism.

3 . The system of claim 2 , wherein the start command also comprises information about the one or more functions to be executed by the accelerator.

4 . The system of claim 1 , wherein the processor core is located on a first chip, and wherein the accelerator is located on the first chip, on the processor core, or on a second chip that is operatively coupled to the first chip.

5 . The system of claim 1 , wherein the accelerator is an artificial intelligence (AI) processing unit.

6 . The system of claim 1 , further comprising:

a monitoring component that:

accesses the one or more messages; and

monitors the running state of the accelerator at the cache, based on the one or more messages.

7 . The system of claim 6 , further comprising:

an inferencing component that:

determines, based on the monitoring, whether the running state indicates an updated state of the accelerator as compared to a previously recorded running state of the accelerator;

determines, based on the running state, a phase of the program being executed by the processor core; and

determines, based on the phase, whether the accelerator has completed execution of the one or more functions.

8 . The system of claim 7 , wherein the selection component acquires a lock for the accelerator after selecting the accelerator and releases the lock based on a determination that the accelerator has completed the execution of the one or more functions.

9 . A computer-implemented method, comprising:

selecting, by a system operatively coupled to a processor, an accelerator to execute one or more functions related to a program being executed by a processor core; and

transmitting, by the system, an address associated with a cache to the accelerator, wherein the address is transmitted within a start command from the processor core to the accelerator via a signaling bus that is directly connected between the processor core and the accelerator, wherein the cache is accessible to both the processor core and the accelerator, and wherein the address is employable by the accelerator to install one or more messages in the cache via non-cached stores to communicate a running state of the accelerator to the processor core during execution of the one or more functions.

10 . The computer-implemented method of claim 9 , wherein the start command is transmitted from the processor core to the accelerator via a sideband signaling mechanism.

11 . The computer-implemented method of claim 10 , wherein the start command also comprises information about the one or more functions to be executed by the accelerator.

12 . The computer-implemented method of claim 9 , wherein the processor core is located on a first chip, and wherein the accelerator is located on the first chip, on the processor core, or on a second chip that is operatively coupled to the first chip.

13 . The computer-implemented method of claim 9 , wherein the accelerator is an AI processing unit.

14 . The computer-implemented method of claim 9 , further comprising:

accessing, by the system, the one or more messages; and

monitoring, by the system, the running state of the accelerator at the cache, based on the one or more messages.

15 . The computer-implemented method of claim 14 , further comprising:

determining, by the system, based on the monitoring, whether the running state indicates an updated state of the accelerator as compared to a previously recorded running state of the accelerator;

determining, by the system, based on the running state, a phase of the program being executed by the processor core; and

determining, by the system, based on the phase, whether the accelerator has completed execution of the one or more functions.

16 . The computer-implemented method of claim 15 , further comprising:

acquiring, by the system, a lock for the accelerator after the selecting; and

releasing, by the system, the lock based on a determination that the accelerator has completed the execution of the one or more functions.

17 . A computer program product for communication between a processor core and an accelerator, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

select, by the processor, the accelerator to execute one or more functions related to a program being executed by the processor core; and

transmit, by the processor, an address associated with a cache to the accelerator, wherein the address is transmitted within a start command from the processor core to the accelerator via a signaling bus that is directly connected between the processor core and the accelerator, wherein the cache is accessible to both the processor core and the accelerator, and wherein the address is employable by the accelerator to install one or more messages in the cache via non-cached stores to communicate a running state of the accelerator to the processor core during execution of the one or more functions.

18 . The computer program product of claim 17 , wherein the start command is transmitted from the processor core to the accelerator via a sideband signaling mechanism.

Assignments (1)

Continuity (1)

References Cited (27)