LOW POWER FLIP-FLOP CIRCUIT
Aspects for a flip-flop circuit are described herein. As an example, the aspects may include a first passgate, a first latch, a second passgate, and a second latch. The first latch may include a first inverter and a first logic gate. The first logic gate may further include a second inverter and at least one voltage reducing component. The voltage reducing component may be an N-channel transistor or a P-channel transistor. Similarly, the second latch may include a third inverter and a second logic gate. The second logic gate may further include a fourth inverter and at least one voltage reducing component.
1 . A latch circuit, comprising:
a first inverter that includes
a first input terminal coupled to a first node, and
a first output terminal coupled to a second node; and
a logic gate that includes
a second input terminal coupled to the second node, and
a second output terminal coupled to the first node,
wherein the logic gate includes at least one voltage reducing component and a second inverter,.
wherein the at least one voltage reducing component includes a transistor and a gate terminal of the transistor is coupled to a source terminal or a drain terminal of the transistor,
wherein an input terminal of the second inverter is coupled to the second node, and
wherein an output terminal of the second inverter is coupled to the first node.
2 . The latch circuit of claim 1 , wherein the transistor included in the at least one voltage reducing component is a P-channel transistor
3 . The latch circuit of claim 1 , wherein the transistor included in the at least one voltage reducing component is a N-channel transistor
4 . The latch circuit of claim 1 , wherein the at least one voltage reducing component is coupled between a supply terminal and a voltage terminal of the second inverter.
5 . The latch circuit of claim 1 , wherein the at least one voltage reducing component is coupled between a ground point and a ground terminal of the second inverter.