Technologies for providing multiple levels of error correction
Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.
1. A memory comprising:
media access circuitry coupled to a memory media, wherein the media access circuitry is to:
read data from the memory media; and
perform, with an error-correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data, wherein the error correction logic unit is different from a second error correction logic unit located in a memory controller and to perform error correction on the read data comprises to perform, with the error-correction logic unit configured to operate on a smaller data set than the second error correction logic unit, the error correction.
2. The memory of claim 1 , wherein to perform error correction on the read data comprises to perform, with the error-correction logic unit located on the same die as the memory media, the error correction on the read data.
3. The memory of claim 1 , wherein to perform error correction on the read data comprises to perform the error correction on data from four partitions of the memory media.
4. The memory of claim 1 , wherein to perform error correction on the read data comprises to perform the error correction on 512 bits of read data.
5. The memory of claim 1 , wherein the memory further comprises a memory controller and the memory controller is to perform additional error correction on the error-corrected data.
6. The memory of claim 5 , wherein the memory controller is further to provide, to a processor of a compute device in which the memory is located, the error-corrected data.
7. The memory of claim 1 , wherein to read data from the memory media comprises to read data from a memory media having a cross point architecture.
8. The memory of claim 7 , wherein to read data from the memory media comprises to read data from a memory media having a three dimensional cross point architecture.
9. The memory of claim 1 , wherein the media access circuitry is further to write the error-corrected data to a scratch pad.
10. The memory of claim 1 , wherein the media access circuitry is further to perform an in-memory compute operation on the error-corrected data.
11. The memory of claim 10 , wherein to perform an in-memory compute operation on the error-corrected data comprises to perform a tensor operation on the error-corrected data.
12. The memory of claim 1 , wherein the media access circuitry is formed from a complementary metal-oxide-semiconductor (CMOS).
13. A method comprising:
reading, by media access circuitry coupled to a memory media, data from the memory media; and
performing, by an error-correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data, wherein the error correction logic unit is different from a second error correction logic unit located in a memory controller and to perform error correction on the read data comprises performing, by the error-correction logic unit configured to operate on a smaller data set than the second error correction logic unit, the error correction.
14. The method of claim 13 , wherein performing error correction on the read data comprises performing, by an error-correction logic unit located on the same die as the memory media, the error correction on the read data.
15. The method of claim 13 , wherein performing error correction on the read data comprises performing the error correction on data from four partitions of the memory media.
16. The method of claim 13 , wherein performing error correction on the read data comprises performing the error correction on 512 bits of read data.