Organic light emitting diode (OLED) compensation circuit, display panel and display apparatus
An organic light-emitting diode (OLED) compensation circuit, a display panel and a display apparatus are provided. The OLED compensation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a storage capacitor and an OLED element. For the first transistor, a gate electrode is electrically connected to a first scanning signal line, a first electrode electrically connected to a data signal line, and a second electrode electrically connected to a first node. For the second transistor, a gate electrode is electrically connected to a first light-emitting control signal line, a first electrode electrically connected to a first voltage signal line, and a second electrode electrically connected to a second node. For the third transistor, a gate electrode is electrically connected to the first node, a first electrode electrically connected to the second node, and a second electrode electrically connected to a third node.
1. An organic light-emitting diode (OLED) compensation circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a storage capacitor; and
an OLED element,
wherein:
a gate electrode of the first transistor is electrically connected to a first scanning signal line, a first electrode of the first transistor is electrically connected to a data signal line, and a second electrode of the first transistor is electrically connected to a first node;
a gate electrode of the second transistor is electrically connected to a first light-emitting control signal line, a first electrode of the second transistor is electrically connected to a first voltage signal line, and a second electrode of the second transistor is electrically connected to a second node;
a gate electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the second node, and a second electrode of the third transistor is electrically connected to a third node;
a gate electrode of the fourth transistor is electrically connected to a first control signal line, a first electrode of the fourth transistor is electrically connected to a sensing signal line, and a second electrode of the fourth transistor is electrically connected to the second node;
a first plate of the storage capacitor is electrically connected to the first node, and a second plate of the storage capacitor is electrically connected to the second node;
a first electrode of the OLED element is electrically connected to the third node, and a second electrode of the OLED element is electrically connected to a second voltage signal line;
a gate electrode of the fifth transistor is electrically connected to a second scanning signal line, a first electrode of the fifth transistor is electrically connected to a reference voltage signal line, and a second electrode of the fifth transistor is electrically connected to the third node; and
a gate electrode of the sixth transistor is electrically connected to a second light-emitting control signal line, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to an anode of the OLED element.
2. The OLED compensation circuit according to claim 1 ,
wherein:
the first transistor, the second transistor, the third transistor and the fourth transistor are PMOS transistors.
3. The OLED compensation circuit according to claim 2 , wherein a compensation stage of the OLED compensation circuit comprises a first stage, a second stage, a third stage and a fourth stage, wherein:
during the first stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the first control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the second stage, a low voltage level signal is supplied to the first scanning signal line, a low voltage level signal is supplied to the first control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line, and a sensing voltage signal is carried by the sensing signal line,
during the third stage, a low voltage level signal is supplied to the first scanning signal line, a low voltage level signal is supplied to the first control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line, and the sensing signal line is in a high impedance state, and
during the fourth stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the first control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line.
4. The OLED compensation circuit according to claim 2 , wherein a display stage of the OLED compensation circuit comprises a first stage and a second stage, wherein:
during the first stage, a low voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the first control signal line, and a low voltage level signal is supplied to the first light-emitting control signal line, and
during the second stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the first control signal line, and a low voltage level signal is supplied to the first light-emitting control signal line.
5. The OLED compensation circuit according to claim 1 , wherein:
the fifth transistor and the sixth transistor are PMOS transistors.
6. The OLED compensation circuit according to claim 5 , wherein a compensation stage of the OLED compensation circuit comprises a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage, a seventh stage and an eighth stage, wherein:
during the first stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the second stage, a high voltage level signal is supplied to the first scanning signal line, a low voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the third stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the fourth stage, a low voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a low voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the fifth stage, a low voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a low voltage level signal is supplied to the first control signal line, a low voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the sixth stage, a low voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a low voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the seventh stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a low voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line, and
during the eighth stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line.
7. The OLED compensation circuit according to claim 5 , wherein a display stage of the OLED compensation circuit comprises a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage, a seventh stage, an eighth stage and a ninth stage, wherein:
during the first stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a low voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the second stage, a high voltage level signal is supplied to the first scanning signal line, a low voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a low voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the third stage, a high voltage level signal is supplied to the first scanning signal line, a low voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the fourth stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the fifth stage, a low voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a low voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the sixth stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a low voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the seventh stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a high voltage level signal is supplied to the first light-emitting control signal line,
during the eighth stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a high voltage level signal is supplied to the second light-emitting control signal line, and a low voltage level signal is supplied to the first light-emitting control signal line, and
during the ninth stage, a high voltage level signal is supplied to the first scanning signal line, a high voltage level signal is supplied to the second scanning signal line, a high voltage level signal is supplied to the first control signal line, a low voltage level signal is supplied to the second light-emitting control signal line, and a low voltage level signal is supplied to the first light-emitting control signal line.
8. A display panel comprising:
a substrate;
a semiconductor layer of a first transistor disposed on the substrate;
a semiconductor layer of a second transistor disposed on the substrate;
a semiconductor layer of a third transistor disposed on the substrate;
a semiconductor layer of a fourth transistor disposed on the substrate;
a gate insulating layer covering the semiconductor layer of the first transistor, the semiconductor layer of the second transistor, the semiconductor layer of the third transistor and the semiconductor layer of the fourth transistor;
a gate electrode of the first transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the first transistor;
a gate electrode of the second transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the second transistor;
a gate electrode of the third transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the third transistor;
a gate electrode of the fourth transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the fourth transistor;
a first plate of a storage capacitor, disposed on the substrate and overlapped with the gate electrode of the third transistor;
an auxiliary insulating layer covering the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the third transistor, the gate electrode of the fourth transistor and the first plate of the storage capacitor;
a second plate of the storage capacitor, disposed on the substrate and overlapped with the first plate of the storage capacitor;
an interlayer insulating layer covering the second plate of the storage capacitor;
a first scanning signal line disposed on the substrate, extending along a first direction;
a data signal line disposed on the substrate, extending along a second direction, wherein the second direction intersects with the first direction;
a first light-emitting control signal line disposed on the substrate, extending along the first direction;
a first voltage signal line disposed on the substrate, extending along the second direction;
a first control signal line disposed on the substrate, extending along the first direction; and
a sensing signal line disposed on the substrate, extending along the second direction; wherein:
the gate electrode of the first transistor is electrically connected to the first scanning signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first plate of the storage capacitor,
the gate electrode of the second transistor is electrically connected to the first light-emitting control signal line, a first electrode of the second transistor is electrically connected to the first voltage signal line, and a second electrode of the second transistor is electrically connected to the second plate of the storage capacitor,
the gate electrode of the third transistor is electrically connected to the first plate of the storage capacitor and a first electrode of the third transistor is electrically connected to the second plate of the storage capacitor, and
the gate electrode of the fourth transistor is electrically connected to the first control signal line, a first electrode of the fourth transistor is electrically connected to the sensing signal line, and a second electrode of the fourth transistor is electrically connected to the second plate of the storage capacitor.
9. The display panel according to claim 8 , wherein:
the first scanning signal line, the first light-emitting control signal line, the first control signal line and the first plate of the storage capacitor are disposed on a first metal layer,
the data signal line, the sensing signal line and the first voltage signal line are disposed on a second metal layer, and
the second plate of the storage capacitor is disposed on an auxiliary metal layer.
10. The display panel according to claim 9 , wherein:
the second plate of the storage capacitor is disposed on the auxiliary metal layer, and the auxiliary metal layer is located between the first metal layer and the second metal layer.
11. The display panel according to claim 8 , further comprising a fifth transistor and a sixth
transistor, wherein:
a semiconductor layer of the fifth transistor is disposed on the substrate,
a semiconductor layer of the sixth transistor is disposed on the substrate,
the gate insulating layer covers the semiconductor layer of the fifth transistor and the semiconductor layer of the sixth transistor,
a gate electrode of the fifth transistor is disposed on the gate insulating layer and overlapped with the semiconductor layer of the fifth transistor,
a gate electrode of the sixth transistor is disposed on the gate insulating layer and overlapped with the semiconductor layer of the sixth transistor,
the auxiliary insulating layer covers the gate electrode of the fifth transistor and the gate electrode of the sixth transistor,
a second scanning signal line, disposed on the substrate, extends along the first direction, and
a reference voltage signal line, disposed on the substrate, extends along the first direction.
12. The display panel according to claim 11 , wherein:
the second scanning signal line and the first scanning signal line are disposed on a same layer, and
the reference voltage signal line and the second plate of the storage capacitor are disposed on a same layer.
13. The display panel according to claim 8 , comprising a plurality of sub-pixels arranged in a
matrix, wherein:
each of the plurality of sub-pixels includes an organic light-emitting diode (OLED) compensation circuit,
the OLED compensation circuit includes the first transistor, the second transistor, the third transistor, the fourth transistor, the storage capacitor and an OLED element, and
for each of the plurality of sub-pixels arranged in a same column, the first electrode of the first transistor is electrically connected to a same sensing signal line.
14. A display apparatus comprising a display panel, wherein the display panel comprises:
a substrate;
a semiconductor layer of a first transistor disposed on the substrate;
a semiconductor layer of a second transistor disposed on the substrate;
a semiconductor layer of a third transistor disposed on the substrate;
a semiconductor layer of a fourth transistor disposed on the substrate;
a gate insulating layer covering the semiconductor layer of the first transistor, the semiconductor layer of the second transistor, the semiconductor layer of the third transistor and the semiconductor layer of the fourth transistor;
a gate electrode of the first transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the first transistor;
a gate electrode of the second transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the second transistor;
a gate electrode of the third transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the third transistor;
a gate electrode of the fourth transistor, disposed on the gate insulating layer and overlapped with the semiconductor layer of the fourth transistor;
a first plate of a storage capacitor, disposed on the substrate and overlapped with the gate electrode of the third transistor;
an auxiliary insulating layer covering the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the third transistor, the gate electrode of the fourth transistor and the first plate of the storage capacitor;
a second plate of the storage capacitor, disposed on the substrate and overlapped with the first plate of the storage capacitor;
an interlayer insulating layer covering the second plate of the storage capacitor;
a first scanning signal line disposed on the substrate, extending along a first direction;
a data signal line disposed on the substrate, extending along a second direction, wherein the second direction intersects with the first direction;
a first light-emitting control signal line disposed on the substrate, extending along the first direction;
a first voltage signal line disposed on the substrate, extending along the second direction;
a first control signal line disposed on the substrate, extending along the first direction; and
a sensing signal line disposed on the substrate, extending along the second direction; wherein:
the gate electrode of the first transistor is electrically connected to the first scanning signal line, a first electrode of the first transistor is electrically connected to the data signal line, and a second electrode of the first transistor is electrically connected to the first plate of the storage capacitor,
the gate electrode of the second transistor is electrically connected to the first light-emitting control signal line, a first electrode of the second transistor is electrically connected to the first voltage signal line, and a second electrode of the second transistor is electrically connected to the second plate of the storage capacitor,
the gate electrode of the third transistor is electrically connected to the first plate of the storage capacitor and a first electrode of the third transistor is electrically connected to the second plate of the storage capacitor, and
the gate electrode of the fourth transistor is electrically connected to the first control signal line, a first electrode of the fourth transistor is electrically connected to the sensing signal line, and a second electrode of the fourth transistor is electrically connected to the second plate of the storage capacitor.
15. The display apparatus according to claim 14 , wherein:
the display panel further includes a fifth transistor and a sixth transistor,
a semiconductor layer of the fifth transistor is disposed on the substrate,
a semiconductor layer of the sixth transistor is disposed on the substrate,
the gate insulating layer covers the semiconductor layer of the fifth transistor and the semiconductor layer of the sixth transistor,
a gate electrode of the fifth transistor is disposed on the gate insulating layer and overlapped with the semiconductor layer of the fifth transistor,
a gate electrode of the sixth transistor is disposed on the gate insulating layer and overlapped with the semiconductor layer of the sixth transistor,
the auxiliary insulating layer covers the gate electrode of the fifth transistor and the gate electrode of the sixth transistor,
a second scanning signal line, disposed on the substrate, extends along the first direction, and
a reference voltage signal line, disposed on the substrate, extends along the first direction.
16. The display apparatus according to claim 14 , wherein:
the display panel includes a plurality of sub-pixels arranged in a matrix,
each of the plurality of sub-pixels includes an organic light-emitting diode (OLED) compensation circuit,
the OLED compensation circuit includes the first transistor, the second transistor, the third transistor, the fourth transistor, the storage capacitor and an OLED element, and
for each of the plurality of sub-pixels arranged in a same column, the first electrode of the first transistor is electrically connected to a same sensing signal line.