Semiconductor memory device and structure
A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.
1. A semiconductor device, the device comprising:
a plurality of memory cells; and
peripheral circuits, said peripheral circuits comprise controlling said plurality of memory cells,
wherein each of said plurality of memory cells comprises a first gate and a second gate,
wherein said plurality of memory cells each comprise a channel region, at least one channel facet, a charge trap region and a tunneling region,
wherein a portion of said peripheral circuits are designed to control said first gate and said second gate so to position two distinct memory sites, a first memory site and second a memory site, within said charge trap region of said at least one channel facet of at least one of said plurality of memory cells, and
wherein said first memory site is substantially closer to said first gate than said second memory site.
2. The semiconductor device according to claim 1 ,
wherein said memory cells each comprise a thick tunneling region of greater than 2 nm thickness.
3. The semiconductor device according to claim 1 ,
wherein control paths from said peripheral circuits to said memory cells comprise a junction-less transistor (“JLT”).
4. The semiconductor device according to claim 1 ,
wherein said second memory site is substantially closer to said second gate than said first memory site.
5. The semiconductor device according to claim 1 ,
wherein said memory cells each comprise a thin tunneling region of less than 1 nm thickness.
6. The semiconductor device according to claim 1 ,
wherein at least one of said memory cells functions as a volatile floating body memory cell.
7. The semiconductor device according to claim 1 ,
wherein said memory cells each comprise a first cell and a second cell sharing the same word-line or the same bit-line, and
wherein said peripheral circuits are structured to conduct a direct transfer of data from said first cell to said second cell using said same word-line or said same bit-line.
8. A semiconductor device, the device comprising:
a plurality of memory cells; and
peripheral circuits, said peripheral circuits comprise controlling said plurality of memory cells,
wherein each of said plurality of memory cells comprises a first gate, a second gate, a channel region, at least a first channel facet overlaid by a first charge trap region and a first gate region, and second channel facet overlaid by a second charge trap region and a second gate region,
wherein a portion of said peripheral circuits are designed to control said first gate and said second gate so to position two distinct memory sites, a first memory site and a second memory site, within said first charge trap region, and
wherein said first memory site is substantially closer to said first gate than said second memory site.
9. The semiconductor device according to claim 8 ,
wherein said second memory cells each comprise a thick tunneling region of greater than 2 nm thickness.
10. The semiconductor device according to claim 8 ,
wherein control paths from said peripheral circuits to said plurality of memory cells comprise a junction-less transistor (“JLT”).
11. The semiconductor device according to claim 8 ,
wherein said second memory site is substantially closer to said second gate than to said first memory site.
12. The semiconductor device according to claim 8 ,
wherein said plurality of memory cells each comprise a thin tunneling region of less than 1 nm thickness.
13. The semiconductor device according to claim 8 ,
wherein at least one of said memory cells functions also as volatile floating body memory cell.
14. The semiconductor device according to claim 8 ,
wherein said plurality of memory cells each comprise a first cell and a second cell sharing the same word-line or the same bit-line, and
wherein said peripheral circuits are structured to conduct a direct transfer of data from said first cell to said second cell using said same word-line or said same bit-line.
15. A semiconductor device, the device comprising:
a plurality of memory cells; and
peripheral circuits, said peripheral circuits comprise controlling said plurality of memory cells,
wherein each of said plurality of memory cells comprises a first gate and a second gate,
wherein said plurality of memory cells each comprise a channel region, at least one channel facet, a charge trap region and a tunneling region,
wherein a portion of said peripheral circuits are designed to control said first gate and said second gate so to position three distinct memory sites within said charge trap region of said at least one channel facet of at least one of said memory cells.
16. The semiconductor device according to claim 15 ,
wherein said memory cells each comprise a thick tunneling region of greater than 2 nm thickness.
17. The semiconductor device according to claim 15 ,
wherein control paths from said peripheral circuits to said plurality of memory cells comprise a junction-less transistor (“JLT”).
18. The semiconductor device according to claim 15 ,
wherein said three distinct memory sites each comprise a first memory site, a second memory site and a third memory site, and
wherein said first memory site is substantially closer to said first gate than said second memory site.
19. The semiconductor device according to claim 15 ,
wherein said memory cells each comprise a thin tunneling region of less than 1 nm thickness.
20. The semiconductor device according to claim 15 ,
wherein said plurality of memory cells each comprise a first cell and a second cell sharing the same word-line or the same bit-line, and
wherein said peripheral circuits are structured to conduct a direct transfer of data from said first cell to said second cell using said same word-line or said same bit-line.