Comparator offset calibration system and analog-to-digital converter with comparator offset calibration

1. A comparator offset calibration system, comprising:

a comparator offset evaluator, receiving digital data from an analog-to-digital conversion module which comprises a comparator, evaluating an offset of the comparator based on the received digital data, and outputting an evaluated result; and

a switched-capacitor network, processing the evaluated result to generate a control signal,

wherein:

the comparator offset evaluator outputs the evaluated result in a pulse width modulation form;

the comparator offset evaluator evaluates the offset of the comparator by long-term judgment of the received digital data; and

the analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

2. The comparator offset calibration system as claimed in claim 1 , wherein:

the comparator offset evaluator uses an accumulation module to transform a series of judgment values obtained by the long-term judgment to the evaluated result that is in the pulse width modulation form; and

the evaluated result in the pulse width modulation form is retrieved from a carry-out output of the accumulation module.

3. The comparator offset calibration system as claimed in claim 2 , wherein:

the comparator offset evaluator repeats mean value calculation on the received digital data periodically to generate a series of mean values and performs mean value judgment on the series of mean values.

4. The comparator offset calibration system as claimed in claim 3 , wherein:

the comparator offset evaluator performs the mean value judgment by comparing the series of mean values with a reference value and thereby generates the series of judgment values.

5. The comparator offset calibration system as claimed in claim 4 , wherein:

the digital data is N bits, where N is a number; and

the reference value is (2 N −1)/2.

6. The comparator offset calibration system as claimed in claim 1 , further comprising:

a calibration circuit provided within the analog-to-digital conversion module,

wherein:

the comparator has an input pair;

the calibration circuit is an auxiliary input pair provided for the comparator, and the auxiliary input pair receives the control signal; and

the control signal is in a differential form.

7. The comparator offset calibration system as claimed in claim 6 , wherein:

the switched-capacitor network uses a first switched-capacitor filter and a second switched-capacitor filter to generate the control signal that is in the differential form.

8. The comparator offset calibration system as claimed in claim 7 , wherein:

the comparator offset evaluator obtains a first series of judgment values and a second series of judgment values by the long-term judgment;

the comparator offset evaluator uses a first accumulator to accumulate the first series of judgment values and uses a second accumulator to accumulate the second series of judgment values; and

a first carry out bit of the first accumulator is coupled to the first switched-capacitor filter and a second carry out bit of the second accumulator is coupled to the second switched-capacitor filter.

9. The comparator offset calibration system as claimed in claim 8 , wherein:

the comparator offset evaluator repeats mean value calculation on the received digital data periodically to generate a series of mean values and performs mean value judgment on the series of mean values.

10. The comparator offset calibration system as claimed in claim 9 , wherein:

the comparator offset evaluator performs the mean value judgment by comparing the series of mean values with a reference value and thereby generates the first series of judgment values and the second series of judgment values.

11. The comparator offset calibration system as claimed in claim 10 , wherein:

the digital data is N bits, where N is a number; and

the reference value is (2 N −1)/2.

12. The comparator offset calibration system as claimed in claim 8 , wherein:

the first accumulator and the second accumulator operate according to a first clock;

the first switched-capacitor filter and the second switched-capacitor filter operate according to the first clock and a second clock; and

the second clock has non-overlapped activation intervals with the first clock.

13. The comparator offset calibration system as claimed in claim 7 , wherein:

the first switched-capacitor filter and the second switched-capacitor filter are multi-stage filters.

14. The comparator offset calibration system as claimed in claim 1 , wherein:

the comparator offset evaluator down-samples the received digital data to ease the long-term judgment.

15. An analog-to-digital converter, comprising:

an analog-to-digital conversion module, comprising at least one comparator;

a comparator offset evaluator, receiving digital data from the analog-to-digital conversion module, evaluating an offset of the at least one comparator based on the received digital data, and outputting evaluated result; and

a switched-capacitor network, processing the evaluated result to generate a control signal,

wherein:

the analog-to-digital conversion module adjusts the offset of the comparator according to the control signal,

the analog-to-digital conversion module comprises a first comparator and a second comparator; and

the first comparator and the second comparator share the comparator offset evaluator and the switched-capacitor network.