Semiconductor structure having both enhancement mode group III-N high electron mobility transistors and depletion mode group III-N high electron mobility transistors

1. An Enhancement-Mode HEMT, comprising:

a pair of stacked Group III-Nitride semiconductor layers, the pair of stacked Group III-Nitride semiconductor layers forming a heterojunction with a 2DEG channel being formed in a lower one of the pair of stacked Group III-Nitride layers;

a source electrode disposed over an upper one of the pair of stacked Group III-Nitride layers;

a drain electrode disposed over an upper one of the pair of stacked Group III-Nitride layers;

a gate electrode disposed between the source electrode and drain electrode, the gate electrode comprising:

a layer of Group-III Nitride material having a dopant; disposed between an electrically conductive gate electrode contact and extending into an upper one on the pair of stacked Group III-Nitride layers such dopant providing the layer with a resistivity greater than the predetermined resistivity of the Group III-Nitride material, the gate electrode contact in Schottky contact with the layer of beryllium doped Group-III Nitride material and depleting carriers from the 2DEG channel under the gate at zero bias condition.

2. An Enhancement-Mode HEMT comprising:

a gate electrode disposed between a source electrode and a drain electrode, the gate electrode comprising:

a layer, disposed between an electrically conductive gate electrode contact and a pair of stacked Group III-Nitride semiconductor layers, the pair of stacked Group III-Nitride semiconductor layers forming a heterojunction with a 2DEG channel being formed in a lower one of the pair of stacked Group III-Nitride layers

such layer comprising: a Group III-N material, the Group III-N material having a predetermined resistivity and a beryllium dopant disposed in the Group III-N material, such beryllium dopant providing the layer with a resistivity greater than the predetermined resistivity of the Group III-N material, and depleting carriers from the 2DEG channel under the gate electrode when an applied gate voltage is less than a threshold voltage.

3. The HEMT recited in claim 1 wherein the dopant is Beryllium.

4. The HEMT recited in claim 1 wherein the dopant is Molecular Beam Epitaxy Beryllium.

5. The HEMT recited in claim 2 wherein the gate electrode extends into an upper one of the pair of stacked Group III-Nitride semiconductor layers.

6. The HEMT recited in claim 2 wherein the beryllium dopant is Molecular Beam Epitaxy Beryllium.

7. An Enhancement-Mode HEMT, comprising:

a crystal structure having a pair of stacked Group III-N semiconductor layers, the pair of stacked Group III-N semiconductor layers forming a heterojunction with a 2DEG channel being formed in a lower one of the pair of stacked Group III-N layers

a source electrode for supplying current to the 2DEG channel;

a drain electrode for extracting current supplied current from the 2DEG channel; and

a gate electrode, disposed between the source electrode and the drain electrode and over the pair of stacked Group III-N semiconductor layers for controlling the supplied current passing to the drain electrode;

such gate electrode; comprising:

an electrically conductive gate electrode contact; and

a doped; Group III-N material; disposed between the electrically conductive gate electrode contact and extending into an upper one of the pair of stacked Group III-N semiconductor layer, such doped, Group III-N material increasing resistivity of the Group III-N material and provides the HEMT with a threshold voltage greater than zero.

8. The structure recited in claim 7 wherein the doped, Group III-N material forces the Fermi level in the doped Group III-N material to reside close enough to the valance band edge to raise the conduction band at the interface between the pair of stacked Group III-N semiconductor layers to deplete carriers from the portion of the 2DEG channel under the gate contact at zero bias condition.

9. The structure recited in claim 7 wherein the doped, Group III-N material is grown by Molecular Beam Epitaxy.

10. The structure recited in claim 7 wherein the gate electrode comprises a single doped, Group III-N material.

11. The structure recited in claim 8 wherein the doped, Molecular Beam Epitaxy Group III-N material comprises Beryllium.

12. An Enhancement-Mode HEMT structure comprising a gate electrode disposed between a source electrode and a drain electrode, the gate electrode comprising;

a doped, Group III-N material disposed between an electrically conductive gate electrode contact and extending into an upper one of a pair of stacked Group III-N semiconductor layer such doped, Group III-N layer increasing resistivity of the Group III-N material and depleting 2DEG channel under the gate electrode at zero bias.

13. An Enhancement-Mode HEMT comprising a gate electrode with a layer of doped; Group III-N material disposed between an electrically conductive gate electrode contact and an upper one of a pair of stacked Group III-N semiconductor layers, such doped; Group III-N layer increasing resistivity of the Group III-N material and depleting carriers from a 2DEG channel under the gate electrode when an applied gate voltage is less than a threshold voltage, and the threshold voltage is greater than zero, the doped Group III-N layer having a thickness greater than 250 Å and the upper one of a pair of stacked Group III-N semiconductor layers having a thickness less than 180 Å.

14. A structure, comprising:

a single crystal substrate;

a Depletion mode (D-mode) HEMT and an Enhancement mode (E-mode) HEMT formed on the single crystal substrate; the Enhancement-Mode HEMT having a gate electrode with a doped; Group III-N material disposed between an electrically conductive gate electrode contact and extending into an upper one of a pair of stacked Group III-N semiconductor layers of the Enhancement-Mode HEMT, such doped; Group III-N layer increasing resistivity of the Group III-N material and depleting carriers from a 2DEG channel under the gate when an applied gate voltage is less than a threshold voltage, and the threshold voltage is greater than zero.