IP Library › Granted Patent US 11,238,333
Granted Patent B2
US 11,238,333 · App. 16/380,177 · Granted Feb 1, 2022

STDP with synaptic fatigue for learning of spike-time-coded patterns in the presence of parallel rate-coding

Inventors: Wabe W. Koelmans (Adliswil, CH); Timoleon Moraitis (Zurich, CH); Abu Sebastian (Adliswil, CH); Tomas Tuma (Adliswil, CH)
Assignee: Samsung Electronics Co., Ltd.
G06N3/063G06N3/049G06N3/08G06N3/088G11C11/54G11C13/0004G11C2013/0071G11C2213/79
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Quick Facts
Patent No.
US 11,238,333
App. No.
16/380,177
Granted
Feb 1, 2022
Kind
B2
Abstract

A circuit implementing a spiking neural network that includes a learning component that can learn from temporal correlations in the spikes regardless of correlations in the rates. In some embodiments, the learning component comprises a rate-discounting component. In some embodiments, the learning rule computes a rate-normalized covariance (normcov) matrix, detects clusters in this matrix, and sets the synaptic weights according to these clusters. In some embodiments, a synapse with a long-term plasticity rule has an efficacy that is composed by a weight and a fatiguing component. In some embodiments, A Hebbian plasticity component modifies the weight component and a short-term fatigue plasticity component modifies the fatiguing component. The fatigue component increases with increases in the presynaptic spike rate. In some embodiments, the fatigue component increases are implemented in a spike-based manner. In some embodiments, the Hebbian plasticity is a spike-timing-dependent plasticity (STDP), resulting in a fatiguing STDP (FSTDP) synapse.

Claims (14)

1. A method comprising:

providing, by machine logic, at least one presynaptic artificial neuron generating a sequence of presynaptic spikes having a timing;

providing, by the machine logic, a postsynaptic artificial neuron comprising a membrane potential;

providing, by the machine logic, a learning rule circuit comprising a synaptic efficacy and a synaptic plasticity; and

providing, by the machine logic, the learning rule circuit configured to learn temporal correlations in the respective timing of the presynaptic spikes by discounting, using a rate-normalized covariance matrix, correlations in spike rates associated with the sequence of presynaptic spikes, the discounting including modifying synaptic efficacies for clusters, in the rate-normalized covariance matrix, having covaryinq frequency higher than a preset threshold, and to modify the synaptic efficacy using a learning rule,

wherein:

the learning rule is based on the timing and the spike rates;

the learning rule circuit comprises either: (i) a normalized covariance circuit configured to, using the learning rule, generate the rate-normalized covariance matrix based on the sequence of presynaptic spikes and a clustering circuit configured to modify the synaptic efficacy according to clusters in the normalized covariance matrix, or (ii) at least one plastic synapse that is operatively connected to the at least one presynaptic artificial neuron to receive the sequence of presynaptic spikes and modify the postsynaptic membrane potential based on the synaptic efficacy and the sequence of presynaptic spikes;

the synaptic efficacy comprises a weighting and a rate-normalization, and

the at least one plastic synapse comprises a Hebbian plasticity circuit configured to modify the weighting, and a rate-dependent plasticity circuit configured to modify the rate-normalization;

the Hebbian plasticity circuit comprises a spike-timing-dependent plasticity rule;

the rate-dependent plasticity circuit comprises a fatigue plasticity rule;

the sequence of presynaptic spikes is characterized by a spike rate and the rate-dependent plasticity circuit is configured to, using the fatigue plasticity rule, modify the rate-normalization so that each spike in the sequence of presynaptic spikes has a reduced effect on the membrane potential when the spike rate increases; and

the at least one plastic synapse comprises either: (i) a non-volatile memory element with volatile characteristics that match the fatigue plasticity rule, or (ii) a digital complementary metal oxide semiconductor (CMOS) circuit or an analog CMOS circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 053276/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2019
From: KOELMANS, WABE W.; MORAITIS, TIMOLEON; SEBASTIAN, ABU; TUMA, TOMAS
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048846/0814 →
Continuity (2)
Continuation 15590530 · May 9, 2017
Related Publication 20190236443A1 · Aug 1, 2019